DDR retention lets N5X skip a full DDR re-calibration across a warm reset by reusing previously calibrated PHY data, which significantly shortens warm reboot time. To do this the SPL must, early in boot and before DRAM is usable, locate a known-good backup of the calibration data, verify it, and replay it into the DDR PHY before handoff. Enable the configs that this restore path depends on:
- CONFIG_FS_LOADER / CONFIG_SPL_FS_LOADER: the generic firmware loader is used by the DDR driver (request_firmware_into_buf()) to pull the backup calibration header and data from the QSPI/NAND RAW partition into the OCRAM scratch buffer (SOC64_OCRAM_PHY_BACKUP_BASE). The loader device is resolved through the "firmware-loader" phandle on the DDR node, falling back to /chosen. SPL_FS_LOADER is required because the restore runs in SPL, before DRAM is available. The N5X RAW path binds SPI flash from DT (sfconfig), so CONFIG_SPL_ENV_SUPPORT is not required. - CONFIG_SPL_CRC32: the retention path checksums the calibration payload with crc32_wd_buf() when storing and validating the QSPI backup. SPL must build lib/crc32.c (obj-$(CONFIG_SPL_CRC32)), which is not selected by SHA384. - CONFIG_SHA384: the calibration backup is bound to the current DDR configuration with a SHA-384 digest (sha384_csum_wd() over the DDR handoff image and the mem-clk table). On store the digest is written into the backup header; on restore it is recomputed and compared (is_ddrconfig_hash_match()), so a backup that no longer matches the running DDR / mem-clk configuration is rejected. Enabling SHA384 selects the SHA-512 implementation it is built on, so CONFIG_SHA512_ALGO does not need to be listed explicitly. Init order and failure modes: the restore is best-effort and fully guarded. The buffer load is bounds-checked against the HPS handoff region (SOC64_HANDOFF_BASE) to prevent overflow, the header magic must match, a CRC32 over the data must match, and finally the SHA-384 config hash must match. If any check fails (missing loader, read error, bad magic, CRC or hash mismatch) the backup is discarded and DDR falls back to a normal full calibration, so an invalid or stale backup never corrupts bring-up. These symbols are enabled only after the fs_loader RAW-partition support and the N5X self-refresh / retention restore code that consume them, so the series stays bisectable. The defconfig is kept in canonical savedefconfig order. Signed-off-by: Tien Fong Chee <[email protected]> Signed-off-by: Chen Huei Lok <[email protected]> --- configs/socfpga_n5x_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 2d9456ef435..2119d8f4f4f 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -72,6 +72,8 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_FS_LOADER=y +CONFIG_SPL_FS_LOADER=y CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_SPI_FLASH_ISSI=y @@ -93,4 +95,5 @@ CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y CONFIG_SPL_CRC32=y +CONFIG_SHA384=y # CONFIG_TOOLS_MKEFICAPSULE is not set -- 2.43.7
