[PATCH v2 2/9] clk: rockchip: rk3399: add the clocks the DSI and VOP paths need

[Petr Hodina via B4 Relay]

From: Petr Hodina <petr.hod...@protonmail.com>

Handle SCLK_DPHY_PLL (fixed 24MHz), set_rate for ACLK_VOP0 and
HCLK_VOP0. Add enable/disable for SCLK_DPHY_TX0_CFG and
PCLK_VIO_GRF.

Signed-off-by: Petr Hodina <petr.hod...@protonmail.com>
---
 drivers/clk/rockchip/clk_rk3399.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index 6e87db18be0..0ddd1f20176 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1001,6 +1001,8 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
        case PCLK_WDT:
                rate = rk3399_alive_get_clk(priv->cru);
                break;
+       case SCLK_DPHY_PLL:
+               return 24000000;
        default:
                log_debug("Unknown clock %lu\n", clk->id);
                return -ENOENT;
@@ -1064,6 +1066,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong 
rate)
        case DCLK_VOP1:
                ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
                break;
+       case ACLK_VOP0:
+       case HCLK_VOP0:
        case ACLK_VOP1:
        case HCLK_VOP1:
        case HCLK_SD:
@@ -1168,6 +1172,11 @@ static int __maybe_unused rk3399_clk_set_parent(struct 
clk *clk,
                return rk3399_gmac_set_parent(clk, parent);
        case SCLK_PCIEPHY_REF:
                return rk3399_pciephy_set_parent(clk, parent);
+       case DCLK_VOP1_DIV:
+       case DCLK_VOP0_DIV:
+       case DCLK_VOP1:
+       case DCLK_VOP0:
+               return 0;
        }
 
        debug("%s: unsupported clk %ld\n", __func__, clk->id);
@@ -1261,6 +1270,12 @@ static int rk3399_clk_enable(struct clk *clk)
                if (readl(&priv->cru->clksel_con[18]) & BIT(10))
                        rk_clrreg(&priv->cru->clkgate_con[12], BIT(6));
                break;
+       case SCLK_DPHY_TX0_CFG:
+               rk_clrreg(&priv->cru->clkgate_con[21], BIT(1));
+               break;
+       case PCLK_VIO_GRF:
+               rk_clrreg(&priv->cru->clkgate_con[29], BIT(12));
+               break;
        default:
                debug("%s: unsupported clk %ld\n", __func__, clk->id);
                return -ENOENT;
@@ -1356,6 +1371,12 @@ static int rk3399_clk_disable(struct clk *clk)
                if (readl(&priv->cru->clksel_con[18]) & BIT(10))
                        rk_setreg(&priv->cru->clkgate_con[12], BIT(6));
                break;
+       case SCLK_DPHY_TX0_CFG:
+               rk_setreg(&priv->cru->clkgate_con[21], BIT(1));
+               break;
+       case PCLK_VIO_GRF:
+               rk_setreg(&priv->cru->clkgate_con[29], BIT(12));
+               break;
        default:
                debug("%s: unsupported clk %ld\n", __func__, clk->id);
                return -ENOENT;

-- 
2.55.0