Commit fd1ba2965244 ("drivers: clk: Fix using assigned-clocks in the
node of the clock it sets up"), first included in v2020.01-rc2, added
a clock-uclass post_probe() hook that applies clock controllers own
assigned clocks.
Remove the redundant clk_set_defaults() call from the RK3568 clock
driver probe() ops. Also remove the unused sync_kernel field that only
recorded whether assigned clocks had been applied.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <[email protected]>
---
arch/arm/include/asm/arch-rockchip/cru_rk3568.h | 1 -
drivers/clk/rockchip/clk_rk3568.c | 9 ---------
2 files changed, 10 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
index d72f241d0150..8af2c5be1ba4 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -53,7 +53,6 @@ struct rk3568_clk_priv {
ulong armclk_hz;
ulong armclk_enter_hz;
ulong armclk_init_hz;
- bool sync_kernel;
bool set_armclk_rate;
};
diff --git a/drivers/clk/rockchip/clk_rk3568.c
b/drivers/clk/rockchip/clk_rk3568.c
index 5a05f1b4de00..2b055a5cea81 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -2866,7 +2866,6 @@ static void rk3568_clk_init(struct rk3568_clk_priv *priv)
{
int ret;
- priv->sync_kernel = false;
if (!priv->armclk_enter_hz) {
priv->armclk_enter_hz =
rockchip_pll_get_rate(&rk3568_pll_clks[APLL],
@@ -2905,17 +2904,9 @@ static void rk3568_clk_init(struct rk3568_clk_priv *priv)
static int rk3568_clk_probe(struct udevice *dev)
{
struct rk3568_clk_priv *priv = dev_get_priv(dev);
- int ret;
rk3568_clk_init(priv);
- /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
- ret = clk_set_defaults(dev, 1);
- if (ret)
- debug("%s clk_set_defaults failed %d\n", __func__, ret);
- else
- priv->sync_kernel = true;
-
return 0;
}
--
2.55.0
