This series adds DDR retention support for the Altera eASIC N5X
SoCFPGA. DDR retention keeps the DRAM contents alive across
configuration resets. With retention enabled, U-Boot can skip the
expensive full PHY re-calibration by restoring previously trained
calibration data from a backup in QSPI.
On a cold/POR boot the PHY is trained normally and the calibration data
is stored to the QSPI backup region. On a subsequent configuration reset
with the System Manager retention bit set, U-Boot treats the QSPI backup
as untrusted until integrity checks pass (header magic, bounds, CRC32
over the calibration payload, SHA384 over the DDR configuration).
Restore is fail-closed: any check failure forces a full PHY
recalibration. When the backup matches, U-Boot replays the PHY init
engine (PIE) handoff instead of recalibrating, so the DDR contents are
preserved.
The series is structured as:
- fs_loader: QSPI RAW offset loading, used to fetch the backup
calibration data from flash (patch 1).
- N5X device tree and defconfig plumbing: fs-loader node, calibration
offsets and binding, and the SHA384/FS_LOADER configs required by
the retention path (patches 2 and 5).
- QSPI mailbox handoff before DDR init so the controller is ready when
retention reads the backup (patch 3).
- Core self-refresh / calibration-backup support in sdram_n5x.c
(patch 4), plus robustness fixes: watchdog progress bit, double-bit
ECC re-init, init-hang recovery, error handling and logging cleanups
(patches 6-13).
- mem-clk handoff change detection (patch 14) and PHY init engine
replay on retention restore (patch 15).
Changes in v4:
- Patch 1: reword commit message to QSPI RAW offset load; mention DDR
calibration backup (and optional FPGA) as consumers; convert the
remaining #if CONFIG_IS_ENABLED(DM/BLK) site to if (CONFIG_IS_ENABLED);
fix device_plat kerneldoc title and @field names.
- Patch 2: add F: entry under ARM ALTERA SOCFPGA in MAINTAINERS for
doc/device-tree-bindings/ram/intel,sdr-ctl-n5x.txt; document the
QSPI calibration-restore trust model (sysmgr retention bit + flash
integrity) and fail-closed behaviour in that binding.
- Patch 3: convert CONFIG_CADENCE_QSPI #ifdef to if (IS_ENABLED(...)).
- Patches 4 and 5: reword commit messages from warm reset to
configuration reset for the QSPI calibration-restore path.
- Patch 4: no code change for trust model; fail-closed restore path
already present (documented via binding / cover).
- Patch 14: convert ARCH_SOCFPGA_N5X #if IS_ENABLED around CLOCK
endianness handling to if (IS_ENABLED(...)).
Changes in v3:
- Patch 1: prefer IS_ENABLED(CONFIG_SPI_FLASH) over #ifdef for the
DATA_RAW read and SPI probe paths; gate env_get() with
CONFIG_IS_ENABLED(ENV_SUPPORT) so SPL can build without
CONFIG_SPL_ENV_SUPPORT.
- Patch 2: add doc/device-tree-bindings/ram/intel,sdr-ctl-n5x.txt for
intel,ddrcal-qspi-offset and intel,ddrcal-ddr-offset.
- Patch 5: drop CONFIG_SPL_ENV_SUPPORT; keep CONFIG_SPL_CRC32 for
crc32_wd_buf() used by the retention backup path; enable
CONFIG_SHA384 / FS_LOADER / SPL_FS_LOADER.
Changes in v2:
- Patch 1: drop weak blk_get_by_device stub; keep empty-name reject for
DATA_FS and parse hex offsets only for DATA_RAW; return -ENOSYS when
DATA_RAW is selected without CONFIG_SPI_FLASH; gate SPI probe on
DATA_RAW.
- Patch 4: remove unused BAC_CAL_MMC_RAW_OFFSET; fix FPGA-prefixed
debug message; NULL-check ddrcal DT offsets and fail closed; copy
header + data_len instead of hard-coded SZ_4K.
- Patch 14: replace VLA in populate_memclk_handoff with a fixed-size
array; return false (not -EFAULT) from bool is_ddrconfig_hash_match()
on handoff read failure.
Tested-on: Intel SoCFPGA N5X SoCDK hardware.
Chen Huei Lok (7):
arm: dts: socfpga: n5x: add DDR retention calibration backup nodes
arm: socfpga: n5x: enable QSPI mailbox before DDR init
configs: socfpga: n5x: enable required configs for DDR retention
ddr: altera: n5x: rename is_ddr_init_skipped() and quieten reset log
ddr: altera: n5x: drop always-false unsigned less-than-zero checks
ddr: altera: n5x: reconfigure DDR when mem-clk handoff changes
ddr: altera: n5x: Replay PIE handoff on DDR retention restore
Tien Fong Chee (8):
misc: fs_loader: Add QSPI RAW offset loading support
ddr: altera: n5x: Add self-refresh support in DDR4
ddr: altera: n5x: set DDR init progress bit for watchdog recovery
ddr: altera: n5x: re-init DDR when double-bit ECC error is detected
ddr: altera: n5x: re-init DDR after watchdog reset from init hang
ddr: altera: n5x: return error on invalid DDR controller type
ddr: altera: n5x: use correct cast for reset status register read
ddr: altera: n5x: fix debug log typo
MAINTAINERS | 1 +
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 13 +
.../mach-socfpga/include/mach/handoff_soc64.h | 1 +
.../include/mach/system_manager_soc64.h | 3 +-
arch/arm/mach-socfpga/spl_n5x.c | 7 +-
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 7 +-
configs/socfpga_n5x_defconfig | 3 +
doc/device-tree-bindings/misc/fs_loader.txt | 8 +
.../ram/intel,sdr-ctl-n5x.txt | 44 +
drivers/ddr/altera/sdram_n5x.c | 1079 +++++++++++++++--
drivers/misc/fs_loader.c | 99 +-
include/fs_loader.h | 33 +-
12 files changed, 1140 insertions(+), 158 deletions(-)
create mode 100644 doc/device-tree-bindings/ram/intel,sdr-ctl-n5x.txt
--
2.43.7
