Move the mbox_qspi_open() call ahead of DRAM initialization so the QSPI controller is handed over to the HPS and its reference clock is configured before the DDR retention path reads the calibration backup from QSPI during DDR init.
Signed-off-by: Chen Huei Lok <[email protected]> --- arch/arm/mach-socfpga/spl_n5x.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index 381aca6d32f..bb2d6187ffc 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -105,6 +105,9 @@ void board_init_f(ulong dummy) hang(); } + if (IS_ENABLED(CONFIG_CADENCE_QSPI)) + mbox_qspi_open(); + #if CONFIG_IS_ENABLED(ALTERA_SDRAM) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { @@ -112,8 +115,4 @@ void board_init_f(ulong dummy) hang(); } #endif - -#ifdef CONFIG_CADENCE_QSPI - mbox_qspi_open(); -#endif } -- 2.43.7
