Set the tap granularity selection bit in the ECO register on Versal for reference clock frequencies of 120 MHz and above, for octal SPI to work properly.
Signed-off-by: Ashok Reddy Soma <[email protected]> Signed-off-by: Tejas Bhumkar <[email protected]> Signed-off-by: Padmarao Begari <[email protected]> --- drivers/spi/cadence_qspi.h | 4 ++++ drivers/spi/cadence_qspi_apb.c | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index d97a4cbe9c1..86f2fd639c5 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -33,6 +33,8 @@ #define CQSPI_DUMMY_BYTES_MAX 4 #define CQSPI_DUMMY_CLKS_MAX 31 +#define CQSPI_TAP_GRAN_SEL_MIN_FREQ 120000000 + #define CMD_4BYTE_FAST_READ 0x0C #define CMD_4BYTE_OCTAL_READ 0x7c #define CMD_4BYTE_READ 0x13 @@ -118,6 +120,8 @@ #define CQSPI_REG_IRQSTATUS 0x40 #define CQSPI_REG_IRQMASK 0x44 +#define CQSPI_REG_ECO 0x48 +#define CQSPI_REG_ECO_TAP_GRAN_SEL BIT(0) #define CQSPI_REG_INDIRECTRD 0x60 #define CQSPI_REG_INDIRECTRD_START BIT(0) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e9cd8df2837..f62238647e3 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -381,6 +381,15 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv) << CQSPI_REG_CONFIG_CHIPSELECT_LSB); writel(reg, priv->regbase + CQSPI_REG_CONFIG); + /* + * Versal OSPI needs the tap granularity selection in the ECO + * register for reference clocks of 120 MHz and above. + */ + if (IS_ENABLED(CONFIG_ARCH_VERSAL) && + priv->ref_clk_hz >= CQSPI_TAP_GRAN_SEL_MIN_FREQ) + writel(CQSPI_REG_ECO_TAP_GRAN_SEL, + priv->regbase + CQSPI_REG_ECO); + cadence_qspi_apb_controller_enable(priv->regbase); } -- 2.34.1
