The read and write watermark registers are not initialized. Set the read watermark to half of the FIFO and the write watermark to 1/8 of the FIFO size.
The read watermark indicates that if the SRAM fill level is above this watermark, an interrupt is generated and a read or DMA can be performed. The write watermark indicates the maximum fill level of the SRAM when a write is performed to the device. These values of 1/2 for read and 1/8 for write are chosen similar to the Linux driver. Signed-off-by: Ashok Reddy Soma <[email protected]> Signed-off-by: Tejas Bhumkar <[email protected]> Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> Signed-off-by: Padmarao Begari <[email protected]> --- drivers/spi/cadence_qspi_apb.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index f977dfa08e9..e9cd8df2837 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -361,6 +361,14 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv) /* Indirect mode configurations */ writel(priv->fifo_depth / 2, priv->regbase + CQSPI_REG_SRAMPARTITION); + /* Program read watermark -- 1/2 of the FIFO. */ + writel(priv->fifo_depth * priv->fifo_width / 2, + priv->regbase + CQSPI_REG_INDIRECTRDWATERMARK); + + /* Program write watermark -- 1/8 of the FIFO. */ + writel(priv->fifo_depth * priv->fifo_width / 8, + priv->regbase + CQSPI_REG_INDIRECTWRWATERMARK); + /* Disable all interrupts */ writel(0, priv->regbase + CQSPI_REG_IRQMASK); -- 2.34.1
