Remove the code that explicitly sets the dummy cycles in the
CQSPI_REG_RD_INSTR register during partial reads. Instead, rely on
the value already programmed in the RD_INSTR register for the current
operation. This avoids the data mismatches observed when manually
setting the dummy cycles and ensures compatibility with the flash
device's expected timing.
Fixes: cf553bf20e51 ("arm64: versal: Add versal specific cadence ospi driver")
Signed-off-by: Padmarao Begari <[email protected]>
---
drivers/spi/cadence_ospi_versal.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/spi/cadence_ospi_versal.c
b/drivers/spi/cadence_ospi_versal.c
index 0133c92b60c..680857e5c42 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -110,10 +110,6 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv
*priv,
return ret;
}
- dummy_cycles = 8;
- writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode,
- priv->regbase + CQSPI_REG_RD_INSTR);
-
reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
reg |= (addr_bytes & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
--
2.34.1
