Public bug reported: This series allows for hitless STE update when EATS and MEV change between S2 and S1+S2 modes or different S1+S2 configs, by marking these bits as safe to update so the algorithm no longer forces a breaking STE update (STE.V=0).
LKML: https://lore.kernel.org/linux- iommu/[email protected]/t/#u v7.0: 2781f2a iommu/arm-smmu-v3: Add update_safe bits to fix STE update sequence f3c1d37 iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence 7cad800 iommu/arm-smmu-v3: Mark EATS_TRANS safe when computing the update sequence a4f976e iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage These patches picked clean and were tested by running the following CUDA mergeSort test script from a GB200 GPU passthrough VM with guest kernel parameter iommu.passthrough=1 applied: for i in {0..5000}; do ./mergeSort > /dev/null 2>&1 & ./mergeSort > /dev/null 2>&1 & ./mergeSort > /dev/null 2>&1 & ./mergeSort > /dev/null 2>&1 & ./mergeSort > /dev/null 2>&1 & wait done ** Affects: linux-nvidia-6.17 (Ubuntu) Importance: Undecided Status: New -- You received this bug notification because you are a member of Ubuntu Bugs, which is subscribed to Ubuntu. https://bugs.launchpad.net/bugs/2143862 Title: Backport iommu/arm-smmu-v3: Fix hitless STE update in nesting cases To manage notifications about this bug go to: https://bugs.launchpad.net/ubuntu/+source/linux-nvidia-6.17/+bug/2143862/+subscriptions -- ubuntu-bugs mailing list [email protected] https://lists.ubuntu.com/mailman/listinfo/ubuntu-bugs
