Without a login, I apparently can't look at the schematic of the Embedded
Artist's Dev Kit, so I'm going to be making some assumptions here. The
following example assumes that the QSPI flash is attached to the following pins
(but it's relatively easy to change):
· CS attached to P3.8
· CLK attached to P3.3
· MOSI attached to P3.7
· MISO attached to P3.6
· IO2 attached to P3.5
· IO3 attached to P3.4
Also, you need to confirm how to set the processor to boot from USB0 and from
internal flash. Without the schematic I can't tell you specifically, how
that's done on that board. But for now, set it to USB0 mode.
In u-boot you'll need to create a new board config, folder, config header, and
board.c file. The board.c configures all the I/O, RAM and other peripherals
needed for u-boot to run. I've attached a copy of ours to give you an idea
what needs to be added. I also attached our header file as an example, and
that needs to be placed in the include/configs folder.
You'll definitely need to make changes to both to get things working for your
particular hardware.
Once you compile your new configuration, you'll need to take the u-boot.bin and
program it into the internal flash using DFUSec (which can be found at
lpcware.com). Then power off the board, switch to internal flash boot mode,
and power it up. If you've configured everything correctly, you should see a
console via the UART.
Feel free to ask more specific questions as you go through this process.
Thanks,
Doug Brainard
From: uclinux-dev-boun...@uclinux.org [mailto:uclinux-dev-boun...@uclinux.org]
On Behalf Of Cristobal Chaves
Sent: Saturday, March 21, 2015 4:59 AM
To: uClinux development list
Subject: Re: [uClinux-dev] boot uClinux from a Cortex-M should be simple
I am working with the development kit of embedded artist,but also I'm working
in parallel with a custom hardware, with different dirvers and applications,
although I use the same microcontroller.
All tests do them in the development kit and when I have success then I test my
custom hardware.
Thanks,
Cristobal
________________________________
From: dbrain...@infinisource.com<mailto:dbrain...@infinisource.com>
To: uclinux-dev@uclinux.org<mailto:uclinux-dev@uclinux.org>
Date: Fri, 20 Mar 2015 13:07:19 -0400
Subject: Re: [uClinux-dev] boot uClinux from a Cortex-M should be simple
What hardware are you using? Are you using a development board or a custom
design? If you can try this on some "known good" hardware, then that will make
this easier to work with.
I can suggest u-boot modifications to you once I know more about your platform.
Thanks,
Doug Brainard
From: uclinux-dev-boun...@uclinux.org<mailto:uclinux-dev-boun...@uclinux.org>
[mailto:uclinux-dev-boun...@uclinux.org] On Behalf Of Cristobal Chaves
Sent: Thursday, March 19, 2015 2:25 PM
To: uClinux development list
Subject: Re: [uClinux-dev] boot uClinux from a Cortex-M should be simple
Hi Doug Brainard,
I think if you loaded the u-boot into the internal flash of the LPC4357 and
worked. It is best to follow the steps that you follow, at least be sure it
works.
I've never managed to get anything via USB port, I could not advance so much. I
tried to find other variants, but also without success.
With other real-time operating systems I have worked with my microcontolador,
LPC4357, but I really want to install uClinux, due to all of the advantages, as
you well know.
Thanks in advance,
Cristóbal
________________________________
From: dbrain...@infinisource.com<mailto:dbrain...@infinisource.com>
To: uclinux-dev@uclinux.org<mailto:uclinux-dev@uclinux.org>
Date: Thu, 19 Mar 2015 15:53:30 -0400
Subject: Re: [uClinux-dev] boot uClinux from a Cortex-M should be simple
We load u-boot into the internal flash of the LPC4357. We use QSPI flash for
the Linux image. After u-boot configures the external SDRAM, Linux gets loaded
into it, and then uncompressed and booted.
To do this required some modifications to u-boot from the Emcraft source. I
believe their standard build is made to load u-boot from external NOR flash
(they used the LPC4350) into SRAM. It then configures the SDRAM and loads
Linux from external NOR flash into SDRAM before uncompressing and booting.
Are you getting to the u-boot console? If not, confirm that your boot options
are set for they location you're trying to boot from. That would be the first
thing to check.
If you're getting there, you probably need to modify the SDRAM settings in
u-boot to your specific board memory specifications.
If you can clarify where you are getting stuck, I may be able to provide more
help.
Thanks,
Doug Brainard
From: uclinux-dev-boun...@uclinux.org<mailto:uclinux-dev-boun...@uclinux.org>
[mailto:uclinux-dev-boun...@uclinux.org] On Behalf Of Cristobal Chaves
Sent: Thursday, March 19, 2015 1:35 PM
To: uClinux development list
Subject: Re: [uClinux-dev] boot uClinux from a Cortex-M should be simple
Hi Doug Brainard,
I know the kernel and uboot offered by Emcraft , and also I tried to booting
my microcontroller with this kernel and uboot.
But I have not been successful. You could especificarme exactly the easiest way
to boot the OS, uClinux.
I mean, how I can use that image save and where. So far I've tried to boot from
external memory, from internal flash and through UART, unsuccessfully all
options. I'm not sure if I did it correctly though.
The kerlnel is compiled correctly without errors, according with my hardware.
Thanks in advance,
Cristóbal
________________________________
From: dbrain...@infinisource.com<mailto:dbrain...@infinisource.com>
To: uclinux-dev@uclinux.org<mailto:uclinux-dev@uclinux.org>
Date: Thu, 19 Mar 2015 15:05:23 -0400
Subject: Re: [uClinux-dev] boot uClinux from a Cortex-M should be simple
We're using a variation of it developed by Emcraft for that very same chip. It
currently only uses the M4 portion, but it has worked pretty well for us. The
source code is located at:
https://github.com/EmcraftSystems/linux-emcraft<https://github.com/EmcraftSystems/linux-emcraft>
We also used their expertise to perform a few modifications specific to our
project. I hope that helps get you started.
Thanks,
Doug Brainard
From: uclinux-dev-boun...@uclinux.org<mailto:uclinux-dev-boun...@uclinux.org>
[mailto:uclinux-dev-boun...@uclinux.org] On Behalf Of Cristobal Chaves
Sent: Wednesday, March 18, 2015 12:09 AM
To: uclinux-dev@uclinux.org<mailto:uclinux-dev@uclinux.org>
Subject: [uClinux-dev] boot uClinux from a Cortex-M should be simple
Hi everyone,
I have been working with uClinux on a microcontroller with Cortex-M4/M0,
specifically with LPC4357.
I have to say that I have previously worked with embedded linux, and in this
project I managed properly configure and compile the kernel.
However I am not able to boot uClinux. I think the easiest way is to load the
u-boot directly to the RAM, because I had problems when I tried to boot the OS
from iflash, flash, spiflah, emc8, emc16 or emc32.
All opinions interest me to try to solve the problem. In principle I would like
to boot into core Cortex-M4 and Cortex-M0 in'll try to install another OS more
primitive.
Thanks in advance!
Sincerely,
Cristobal
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/*
* (C) Copyright 2012, 2013, 2014
*
* Alexander Potashev, Emcraft Systems, aspotas...@emcraft.com
* Pavel Boldin, Emcraft Systems, pabol...@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Board specific code for the Embedded Artists LPC4357 OEM board
*/
#include <common.h>
#include <asm/io.h>
#include <netdev.h>
#if defined(CONFIG_SPIFI)
# include <spifi.h>
#endif
#ifdef CONFIG_LCD
# include <lcd.h>
# include <amba_clcd.h>
#endif
#include <asm/arch/lpc18xx_gpio.h>
#include <asm/arch/lpc18xx_scu.h>
#include <asm/arch/lpc18xx_creg.h>
#include <asm/arch/lpc18xx_ccu.h>
#include <asm/arch/lpc18xx_emc.h>
#if (CONFIG_SYS_BOARD_REV == 1)
/*
* MT48LC4M32B2B5-6A SDRAM: 32-bit, 4 banks, 12 row bits, 8 column bits.
* There is typo in current version of LPC43XX UM.
*/
# define LPC18XX_EMC_AM 0x8a
/* 1<<7 | 0<<5 | 2<<2 | 2<<0, typo in LPC4357 UM */
/*
* Timings for MT48LC4M32B2B5-6A memory chip and 204 MHz,
* taken from Infinisource's sample code.
*/
/* Active to read/write delay (RAS latency) */
# define SDRAM_RAS 3 /* From Infinisource's code */
/* CAS latency (CL) */
# define SDRAM_CAS 3 /* CL = 3 */
/* Command delayed strategy, using EMCCLKDELAY */
# define SDRAM_RDCFG_RD 1
/* Precharge command period (tRP) */
# define SDRAM_T_RP NS2CLK(20) /* 20ns */
/* Active to precharge command period (tRAS) */
# define SDRAM_T_RAS NS2CLK(42) /* 42ns */
/* Self-refresh exit time (tSREX) */
# define SDRAM_T_SREX NS2CLK(63) /* We set this to the
same
* as tXSR */
/* Last-data-out to active command time (tAPR) */
# define SDRAM_T_APR NS2CLK(70) /* Not found in the
SDRAM
* datasheet */
/* Data-in to active command (tDAL) */
# define SDRAM_T_DAL (NS2CLK(70) + 1) /* 70ns */
/* Write recovery time (tWR) */
# define SDRAM_T_WR NS2CLK(30) /* 30ns */
/* Active to active command period (tRC) */
# define SDRAM_T_RC NS2CLK(63) /* 63ns */
/* Auto-refresh period and auto-refresh to active command period (tRFC) */
# define SDRAM_T_RFC NS2CLK(63) /* 63ns */
/* Exit self-refresh to active command time (tXSR) */
# define SDRAM_T_XSR NS2CLK(63) /* 70ns */
/* Active bank A to active bank B latency (tRRD) */
# define SDRAM_T_RRD NS2CLK(14) /* 14ns */
/* Load mode register to active command time (tMRD) */
# define SDRAM_T_MRD NS2CLK(30) /* 30ns */
#elif (CONFIG_SYS_BOARD_REV == 2)
/*
* MT48LC8M16A2B4-6A SDRAM (2): 32-bit, 4 banks, 12 row bits, 9 column bits.
*/
# define LPC18XX_EMC_AM 0x89
/* 1<<7 | 0<<5 | 2<<2 | 1<<0 */
/*
* Timings for MT48LC8M16A2B4-6A memory chip and 204 MHz,
* taken from Infinisource's sample code.
*/
/* Active to read/write delay (RAS latency) */
# define SDRAM_RAS 3 /* From Infinisource's code */
/* CAS latency (CL) */
# define SDRAM_CAS 3 /* CL = 3 */
/* Command delayed strategy, using EMCCLKDELAY */
# define SDRAM_RDCFG_RD 1
/* Precharge command period (tRP) */
# define SDRAM_T_RP NS2CLK(18) /* 18ns */
/* Active to precharge command period (tRAS) */
# define SDRAM_T_RAS NS2CLK(42) /* 42ns */
/* Self-refresh exit time (tSREX) */
# define SDRAM_T_SREX NS2CLK(67) /* We set this to the same
* as tXSR */
/* Last-data-out to active command time (tAPR) */
# define SDRAM_T_APR NS2CLK(30) /* Not found in the
SDRAM
* datasheet */
/* Data-in to active command (tDAL) */
# define SDRAM_T_DAL NS2CLK(30) /* 30ns */
/* Write recovery time (tWR) */
# define SDRAM_T_WR NS2CLK(12) /* 12ns */
/* Active to active command period (tRC) */
# define SDRAM_T_RC NS2CLK(60) /* 60ns */
/* Auto-refresh period and auto-refresh to active command period (tRFC) */
# define SDRAM_T_RFC NS2CLK(60) /* 60ns */
/* Exit self-refresh to active command time (tXSR) */
# define SDRAM_T_XSR NS2CLK(67) /* 67ns */
/* Active bank A to active bank B latency (tRRD) */
# define SDRAM_T_RRD NS2CLK(12) /* 12ns */
/* Load mode register to active command time (tMRD) */
# define SDRAM_T_MRD NS2CLK(30) /* 30ns */
#elif (CONFIG_SYS_BOARD_REV == 3)
/*
* AS4C16M16S-6BIN SDRAM (2): 32-bit, 4 banks, 13 row bits, 9 column bits.
*/
# define LPC18XX_EMC_AM 0x8D
/* 1<<7 | 0<<5 | 3<<2 | 1<<0 */
/*
* Timings for AS4C16M16S-6BIN memory chip and 204 MHz,
* taken from Infinisource's sample code.
*/
/* Active to read/write delay (RAS latency) */
# define SDRAM_RAS 3 /* From Infinisource's code */
/* CAS latency (CL) */
# define SDRAM_CAS 3 /* CL = 3 */
/* Command delayed strategy, using EMCCLKDELAY */
# define SDRAM_RDCFG_RD 1
/* Precharge command period (tRP) */
# define SDRAM_T_RP NS2CLK(18) /* 18ns */
/* Active to precharge command period (tRAS) */
# define SDRAM_T_RAS NS2CLK(42) /* 42ns */
/* Self-refresh exit time (tSREX) */
# define SDRAM_T_SREX NS2CLK(62) /* We set this to the same
* as tXSR */
/* Last-data-out to active command time (tAPR) */
# define SDRAM_T_APR NS2CLK(30) /* Not found in the
SDRAM
* datasheet */
/* Data-in to active command (tDAL) */
# define SDRAM_T_DAL NS2CLK(30) /* 30ns */
/* Write recovery time (tWR) */
# define SDRAM_T_WR NS2CLK(12) /* 12ns */
/* Active to active command period (tRC) */
# define SDRAM_T_RC NS2CLK(60) /* 60ns */
/* Auto-refresh period and auto-refresh to active command period (tRFC) */
# define SDRAM_T_RFC NS2CLK(60) /* 60ns */
/* Exit self-refresh to active command time (tXSR) */
# define SDRAM_T_XSR NS2CLK(62) /* 62ns */
/* Active bank A to active bank B latency (tRRD) */
# define SDRAM_T_RRD NS2CLK(12) /* 12ns */
/* Load mode register to active command time (tMRD) */
# define SDRAM_T_MRD NS2CLK(12) /* 12ns */
#endif /* CONFIG_SYS_BOARD_REV == 1 or 2 or 3 */
/*
* Refresh timer.
* Indicates the multiple of 16 CCLKs between SDRAM refresh cycles.
*/
/* (64ms / 4096 row) */
#define SDRAM_REFRESH (NS2CLK(64000000 / 4096) / 16)
/* Only for initialization */
#define SDRAM_REFRESH_FAST 2
/*
* EMC registers
*/
/*
* EMC Control register
*/
#define LPC_EMC_CTRL_EN_MSK (1 << 0)
/*
* Dynamic Memory Control register
*/
/* Dynamic memory clock enable (CE) */
#define LPC_EMC_DYCTRL_CE_MSK (1 << 0)
/* Dynamic memory clock control (CS) */
#define LPC_EMC_DYCTRL_CS_MSK (1 << 1)
/* SDRAM initialization (I) */
#define LPC_EMC_DYCTRL_I_BITS 7
#define LPC_EMC_DYCTRL_I_NORMAL 0
#define LPC_EMC_DYCTRL_I_MODE 1
#define LPC_EMC_DYCTRL_I_PALL 2 /* precharge all */
#define LPC_EMC_DYCTRL_I_NOP 3 /* no operation */
/*
* Dynamic Memory Read Configuration register:
* Read data strategy (RD)
*/
#define LPC_EMC_DYRDCFG_RD_BITS 0
/*
* The SDRAM chip (both MT48LC4M32B2B5-6A and MT48LC8M16A2B4-6A) mode register.
*/
#define SDRAM_MODEREG_BL_BITS 0 /* Burst Length */
#define SDRAM_MODEREG_CAS_BITS 4 /* CAS Latency */
/*
* See both MT48LC4M32B2B5-6A and MT48LC8M16A2B4-6A mode register.
* CAS3, Burst Length = 4.
*/
#define SDRAM_MODEREG_BL 2 /* Burst Length code */
#define SDRAM_MODEREG_CAS 3 /* CAS Latency */
#define SDRAM_MODEREG_VALUE \
((SDRAM_MODEREG_BL << SDRAM_MODEREG_BL_BITS) | \
(SDRAM_MODEREG_CAS << SDRAM_MODEREG_CAS_BITS))
/*
* SDRAM chip-specific options
*/
/*
* From Infinisource' example code.
*/
#if (CONFIG_SYS_BOARD_REV == 1)
/* For MT48LC4M32B2B5-6A */
# define LPC18XX_EMC_MODEREG_ADDR_SHIFT 12
#elif (CONFIG_SYS_BOARD_REV == 2)
/* For MT48LC8M16A2B4-6A */
# define LPC18XX_EMC_MODEREG_ADDR_SHIFT 13
#elif (CONFIG_SYS_BOARD_REV == 3)
/* For AS4C16M16S-6BIN */
# define LPC18XX_EMC_MODEREG_ADDR_SHIFT 13
#endif
/*
* Dynamic Memory registers (per chip)
*/
/*
* Dynamic Memory Configuration register
*/
/* Address mapping */
#define LPC_EMC_DYCFG_AM_BITS 7
/* Buffer enable */
#define LPC_EMC_DYCFG_B_MSK (1 << 19)
/*
* Dynamic Memory RAS & CAS Delay register
*/
/* RAS latency */
#define LPC_EMC_DYRASCAS_RAS_BITS 0
/* CAS latency */
#define LPC_EMC_DYRASCAS_CAS_BITS 8
DECLARE_GLOBAL_DATA_PTR;
/*
* Pin configuration table for Infinisource LPC4357.
*
* This table does not list all MCU pins that will be configured. See also
* the code in `iomux_init()`.
*/
static const struct lpc18xx_pin_config infinisource_lpc4357_iomux[] = {
/*
* Pin configuration for UART
*/
{{CONFIG_LPC18XX_UART_TX_IO_GROUP, CONFIG_LPC18XX_UART_TX_IO_PIN},
LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 0, 0)},
{{CONFIG_LPC18XX_UART_RX_IO_GROUP, CONFIG_LPC18XX_UART_RX_IO_PIN},
LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 1, 0)},
#ifdef CONFIG_LPC18XX_ETH
/*
* Pin configuration for Ethernet (RMII + MDIO)
*/
/* PC.1 = ENET_MDC */
{{0xC, 1}, LPC18XX_IOMUX_CONFIG(3, 0, 0, 1, 1, 0)},
/* P1.17 = ENET_MDIO (high-drive pin) */
{{0x1, 17}, LPC18XX_IOMUX_CONFIG(3, 0, 0, 0, 1, 0)},
/* P1.18 = ENET_TXD0 */
{{0x1, 18}, LPC18XX_IOMUX_CONFIG(3, 0, 0, 1, 1, 0)},
/* P1.20 = ENET_TXD1 */
{{0x1, 20}, LPC18XX_IOMUX_CONFIG(3, 0, 0, 1, 1, 0)},
/* P0.1 = ENET_TX_EN */
{{0x0, 1}, LPC18XX_IOMUX_CONFIG(6, 0, 0, 1, 1, 0)},
/* P1.15 = ENET_RXD0 */
{{0x1, 15}, LPC18XX_IOMUX_CONFIG(3, 0, 0, 1, 1, 0)},
/* P0.0 = ENET_RXD1 */
{{0x0, 0}, LPC18XX_IOMUX_CONFIG(2, 0, 0, 1, 1, 0)},
/* P1.19 = ENET_REF_CLK */
{{0x1, 19}, LPC18XX_IOMUX_CONFIG(0, 0, 0, 1, 1, 0)},
/* P1.16 = ENET_RXDV */
{{0x1, 16}, LPC18XX_IOMUX_CONFIG(7, 0, 0, 1, 1, 0)},
#endif /* CONFIG_LPC18XX_ETH */
#if defined(CONFIG_NR_DRAM_BANKS) || defined(CONFIG_SYS_FLASH_CS)
/*
* EMC pins used for both the SDRAM and the NOR flash memory chips
*/
/* P1.6 = WE# - SDRAM,NOR */
{{0x1, 6}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P2.10 = A1 - SDRAM,NOR */
{{0x2, 10}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P2.11 = A2 - SDRAM,NOR */
{{0x2, 11}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P2.12 = A3 - SDRAM,NOR */
{{0x2, 12}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P2.13 = A4 - SDRAM,NOR */
{{0x2, 13}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P1.0 = A5 - SDRAM,NOR */
{{0x1, 0}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(2)},
/* P1.1 = A6 - SDRAM,NOR */
{{0x1, 1}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(2)},
/* P1.2 = A7 - SDRAM,NOR */
{{0x1, 2}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(2)},
/* P2.8 = A8 - SDRAM,NOR */
{{0x2, 8}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P2.7 = A9 - SDRAM,NOR */
{{0x2, 7}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P2.6 = A10 - SDRAM,NOR */
{{0x2, 6}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(2)},
/* P2.2 = A11 - SDRAM,NOR */
{{0x2, 2}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(2)},
/* P2.1 = A12 - SDRAM,NOR */
{{0x2, 1}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(2)},
/* P2.0 = BA0 for SDRAM (aka A13) - SDRAM,NOR */
{{0x2, 0}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(2)},
/* P6.8 = BA1 for SDRAM (aka A14) - SDRAM,NOR */
{{0x6, 8}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(1)},
/* P1.7 = D0 - SDRAM,NOR */
{{0x1, 7}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.8 = D1 - SDRAM,NOR */
{{0x1, 8}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.9 = D2 - SDRAM,NOR */
{{0x1, 9}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.10 = D3 - SDRAM,NOR */
{{0x1, 10}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.11 = D4 - SDRAM,NOR */
{{0x1, 11}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.12 = D5 - SDRAM,NOR */
{{0x1, 12}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.13 = D6 - SDRAM,NOR */
{{0x1, 13}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.14 = D7 - SDRAM,NOR */
{{0x1, 14}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P5.4 = D8 - SDRAM,NOR */
{{0x5, 4}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.5 = D9 - SDRAM,NOR */
{{0x5, 5}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.6 = D10 - SDRAM,NOR */
{{0x5, 6}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.7 = D11 - SDRAM,NOR */
{{0x5, 7}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.0 = D12 - SDRAM,NOR */
{{0x5, 0}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.1 = D13 - SDRAM,NOR */
{{0x5, 1}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.2 = D14 - SDRAM,NOR */
{{0x5, 2}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.3 = D15 - SDRAM,NOR */
{{0x5, 3}, LPC18XX_IOMUX_EMC_CONFIG(2)},
#endif /* CONFIG_NR_DRAM_BANKS || CONFIG_SYS_FLASH_CS */
#if defined(CONFIG_NR_DRAM_BANKS)
/*
* Configuration for EMC pins used only for SDRAM
*/
/*
* To use 16-bit wide and 32-bit wide SDRAM interfaces, select
* the EMC_CLK function and enable the input buffer (EZI = 1)
* in all four SFSCLKn registers in the SCU.
*/
/* Imaginary P-0x18.0 = CLK (CLK0) - SDRAM */
{{0x18, 0}, LPC18XX_IOMUX_EMC_CONFIG(5)},
/* Imaginary P-0x18.1 = CLK1 - SDRAM */
{{0x18, 1}, LPC18XX_IOMUX_EMC_CONFIG(5)},
/* Imaginary P-0x18.2 = CLK2 - SDRAM */
{{0x18, 2}, LPC18XX_IOMUX_EMC_CONFIG(5)},
/* Imaginary P-0x18.3 = CLK3 - SDRAM */
{{0x18, 3}, LPC18XX_IOMUX_EMC_CONFIG(1)},
/* P6.11 = CKE - SDRAM */
{{0x6, 11}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P6.9 = CS# (nDYCS0) - SDRAM */
{{0x6, 9}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P6.5 = RAS# - SDRAM */
{{0x6, 5}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P6.4 = CAS# - SDRAM */
{{0x6, 4}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P6.12 = DQM0 - SDRAM */
{{0x6, 12}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P6.10 = DQM1 - SDRAM */
{{0x6, 10}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* PD.0 = DQM2 - SDRAM */
{{0xD, 0}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(2)},
/* PE.13 = DQM3 - SDRAM */
{{0xE, 13}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* P2.9 = A0 - SDRAM */
{{0x2, 9}, LPC18XX_IOMUX_EMC_OUTPUT_CONFIG(3)},
/* PD.2 = D16 - SDRAM */
{{0xD, 2}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* PD.3 = D17 - SDRAM */
{{0xD, 3}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* PD.4 = D18 - SDRAM */
{{0xD, 4}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* PD.5 = D19 - SDRAM */
{{0xD, 5}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* PD.6 = D20 - SDRAM */
{{0xD, 6}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* PD.7 = D21 - SDRAM */
{{0xD, 7}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* PD.8 = D22 - SDRAM */
{{0xD, 8}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* PD.9 = D23 - SDRAM */
{{0xD, 9}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* PE.5 = D24 - SDRAM */
{{0xE, 5}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* PE.6 = D25 - SDRAM */
{{0xE, 6}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* PE.7 = D26 - SDRAM */
{{0xE, 7}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* PE.8 = D27 - SDRAM */
{{0xE, 8}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* PE.9 = D28 - SDRAM */
{{0xE, 9}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* PE.10 = D29 - SDRAM */
{{0xE, 10}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* PE.11 = D30 - SDRAM */
{{0xE, 11}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* PE.12 = D31 - SDRAM */
{{0xE, 12}, LPC18XX_IOMUX_EMC_CONFIG(3)},
#endif /* CONFIG_NR_DRAM_BANKS */
#if defined(CONFIG_SPIFI)
/* P3.3 = SPIFI_SCK */
{{0x3, 3}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P3.4 = SPIFI_SIO3 */
{{0x3, 4}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P3.5 = SPIFI_SIO2 */
{{0x3, 5}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P3.6 = SPIFI_MISO */
{{0x3, 6}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P3.7 = SPIFI_MOSI */
{{0x3, 7}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P3.8 = SPIFI_CS */
{{0x3, 8}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 0, 1)},
#endif
#if defined(CONFIG_LCD)
/* RED0->8 */
{{0x4, 1}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0x4, 4}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0x4, 3}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0x4, 2}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0x8, 7}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{{0x8, 6}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{{0x8, 5}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{{0x8, 4}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
/* GREEN0->8 */
{{0x7, 5}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{{0x4, 8}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0x4, 10}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0x4, 9}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0x8, 3}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{{0xB, 6}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0xB, 5}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0xB, 4}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
/* BLUE0->8 */
{{0x7, 4}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{{0x7, 3}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{{0x7, 2}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{{0x7, 1}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{{0xB, 3}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0xB, 2}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0xB, 1}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{{0xB, 0}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
/* LCD_FP (LCD_VSYNC) */
{{0x4, 5}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
/* LCD_ENAB */
{{0x4, 6}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
/* LCD_DCLK */
{{0x4, 7}, LPC18XX_IOMUX_CONFIG(0, 0, 1, 1, 1, 0)},
/* LCD_LP (LCD_HSYNC) */
{{0x7, 6}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
/* LCD_PWR */
{{0x7, 7}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
#endif
};
/*
* Configure all necessary MCU pins
*/
static void iomux_init(void)
{
/*
* Configure GPIO pins using the `infinisource_lpc4357_iomux[]` table
*/
lpc18xx_pin_config_table(infinisource_lpc4357_iomux,
ARRAY_SIZE(infinisource_lpc4357_iomux)
);
}
/*
* Early hardware init.
*/
int board_init(void)
{
/*
* Set SDRAM clock output delay to ~3.5ns (0x7777),
* the SDRAM chip does not work otherwise.
*/
LPC18XX_SCU->emcdelayclk = 0x7777;
/*
* Enable EMC
*/
LPC_EMC->emcctrl = LPC_EMC_CTRL_EN_MSK;
/*
* Little-endian mode
*/
LPC_EMC->emccfg = 0;
/*
* Configure MCU pins
*/
iomux_init();
return 0;
}
/*
* Dump pertinent info to the console.
*/
int checkboard(void)
{
printf("Board: InfiniSource LPC4357\n");
return 0;
}
int validate_uimage(unsigned long addr)
{
image_header_t *hdr = (image_header_t *)addr;
printf("Validating component at offset %08lx\n", addr);
if (genimg_get_format((void *)hdr) != IMAGE_FORMAT_LEGACY) {
puts("Component Boot Image Format is incorrect\n");
return 0;
}
if (!image_check_magic(hdr)) {
puts("Bad Magic Number\n");
return 0;
}
if (!image_check_hcrc(hdr)) {
puts("Bad Header Checksum\n");
return 0;
}
if (!image_check_target_arch(hdr)) {
printf("Unsupported Architecture 0x%x\n", image_get_arch(hdr));
return 0;
}
return 1;
}
int validate_boot_set(int nset)
{
if (!nset) {
return validate_uimage(KERNEL1_FLASH_BASE);
} else {
return validate_uimage(KERNEL2_FLASH_BASE);
}
}
char *simple_itoa(ulong i)
{
/* 21 digits plus null terminator, good for 64-bit or smaller ints */
static char local[22];
char *p = &local[21];
*p-- = '\0';
do {
*p-- = '0' + i % 10;
i /= 10;
} while (i > 0);
return p + 1;
}
/**
* Decode the integer value of an environment variable and return it.
*
* @param name Name of environemnt variable
* @param base Number base to use (normally 10, or 16 for hex)
* @param default_val Default value to return if the variable is not
* found
* @return the decoded value, or default_val if not found
*/
ulong getenv_ulong(const char *name, int base, ulong default_val)
{
/*
* We can use getenv() here, even before relocation, since the
* environment variable value is an integer and thus short.
*/
const char *str = getenv(name);
return str ? simple_strtoul(str, NULL, base) : default_val;
}
/**
* Set an environment variable to an integer value
*
* @param varname Environmet variable to set
* @param value Value to set it to
* @return 0 if ok, 1 on error
*/
int setenv_ulong(const char *varname, ulong value)
{
/* TODO: this should be unsigned */
char *str = simple_itoa(value);
return setenv(varname, str);
}
/**
* Set an environment variable to an address in hex
*
* @param varname Environmet variable to set
* @param addr Value to set it to
* @return 0 if ok, 1 on error
*/
int setenv_addr(const char *varname, const void *addr)
{
char str[17];
sprintf(str, "%x", (uintptr_t)addr);
return setenv(varname, str);
}
int do_validate_boot_images(void)
{
int boot_set1_valid = 0, boot_set2_valid = 0;
int active_boot_set = 0, env_changed = 0;
boot_set1_valid = getenv_ulong("boot_set1_valid", 10, 0);
boot_set2_valid = getenv_ulong("boot_set2_valid", 10, 0);
active_boot_set = getenv_ulong("active_boot_set", 10, -1);
if (active_boot_set != 0 && active_boot_set != 1) {
active_boot_set = -1;
}
if (active_boot_set == 0 &&
(!boot_set1_valid || !validate_boot_set(0))) {
boot_set1_valid = 0;
active_boot_set = boot_set2_valid ? 1 : -1;
env_changed = 1;
}
if (active_boot_set == 1 &&
(!boot_set2_valid || !validate_boot_set(1))) {
boot_set2_valid = 0;
if (!env_changed && boot_set1_valid &&
validate_boot_set(0)) {
active_boot_set = 0;
} else {
boot_set1_valid = 0;
active_boot_set = -1;
}
env_changed = 1;
}
if (env_changed == 0 && active_boot_set == -1) {
if (validate_boot_set(0)) {
boot_set1_valid = 1;
boot_set2_valid = 0;
active_boot_set = 0;
}
else if(validate_boot_set(1)) {
boot_set1_valid = 0;
boot_set2_valid = 1;
active_boot_set = 1;
}
env_changed = 1;
}
if (env_changed) {
setenv_ulong("boot_set1_valid", boot_set1_valid);
setenv_ulong("boot_set2_valid", boot_set2_valid);
setenv_ulong("active_boot_set", active_boot_set);
saveenv();
}
setenv_addr("uImage_backup_offset", (void*)
(!active_boot_set ? KERNEL2_FLASH_BASE : KERNEL1_FLASH_BASE));
setenv_addr("uImage_offset", (void*)
(active_boot_set ? KERNEL2_FLASH_BASE : KERNEL1_FLASH_BASE));
return 0;
}
/*
* Configure board specific parts.
*/
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
#if defined(CONFIG_SPIFI)
if (spifi_initialize()) {
return 1;
}
do_validate_boot_images();
#endif
return 0;
}
#endif /* CONFIG_MISC_INIT_R */
/*
* Setup external RAM.
*/
int dram_init(void)
{
volatile struct lpc_emc_dy_regs *dy;
u32 tmp32;
#ifdef CONFIG_LPC18XX_EMC_HALFCPU
/*
* EMC_CLK_DIV = M4_CLK / 2
*/
LPC18XX_CCU1->clk_m4_emcdiv_cfg |=
LPC18XX_CCU1_CLK_RUN_MSK | LPC18XX_CCU1_CLK_EMCDIV_CFG_DIV2;
LPC18XX_CREG->creg6 |= LPC18XX_CREG_CREG6_EMCCLKSEL_MSK;
LPC18XX_CCU1->clk_m4_emc_cfg |= LPC18XX_CCU1_CLK_RUN_MSK;
#else
#error EMC clock set to M4_CLK/1 is not supported
#endif
LPC_EMC->emcctrl = 0x1;
dy = &LPC_EMC->dy[CONFIG_SYS_RAM_CS];
/*
* Address mapping
*/
dy->cfg = (LPC18XX_EMC_AM << LPC_EMC_DYCFG_AM_BITS);
/*
* Configure DRAM timing
*/
dy->rascas =
(SDRAM_RAS << LPC_EMC_DYRASCAS_RAS_BITS) |
(SDRAM_CAS << LPC_EMC_DYRASCAS_CAS_BITS);
LPC_EMC->dy_rdcfg =
(SDRAM_RDCFG_RD << LPC_EMC_DYRDCFG_RD_BITS);
LPC_EMC->dy_trp = SDRAM_T_RP;
LPC_EMC->dy_tras = SDRAM_T_RAS;
LPC_EMC->dy_srex = SDRAM_T_SREX;
LPC_EMC->dy_apr = SDRAM_T_APR;
LPC_EMC->dy_dal = SDRAM_T_DAL;
LPC_EMC->dy_wr = SDRAM_T_WR;
LPC_EMC->dy_rc = SDRAM_T_RC;
LPC_EMC->dy_rfc = SDRAM_T_RFC;
LPC_EMC->dy_xsr = SDRAM_T_XSR;
LPC_EMC->dy_rrd = SDRAM_T_RRD;
LPC_EMC->dy_mrd = SDRAM_T_MRD;
udelay(100);
/*
* Issue SDRAM NOP (no operation) command
*/
LPC_EMC->dy_ctrl =
LPC_EMC_DYCTRL_CE_MSK | LPC_EMC_DYCTRL_CS_MSK |
(LPC_EMC_DYCTRL_I_NOP << LPC_EMC_DYCTRL_I_BITS);
udelay(200);
/*
* Pre-charge all with fast refresh
*/
LPC_EMC->dy_ctrl =
LPC_EMC_DYCTRL_CE_MSK | LPC_EMC_DYCTRL_CS_MSK |
(LPC_EMC_DYCTRL_I_PALL << LPC_EMC_DYCTRL_I_BITS);
LPC_EMC->dy_rfsh = SDRAM_REFRESH_FAST;
udelay(200);
/*
* Set refresh period
*/
LPC_EMC->dy_rfsh = SDRAM_REFRESH;
/*
* Load mode register
*/
LPC_EMC->dy_ctrl =
LPC_EMC_DYCTRL_CE_MSK | LPC_EMC_DYCTRL_CS_MSK |
(LPC_EMC_DYCTRL_I_MODE << LPC_EMC_DYCTRL_I_BITS);
tmp32 = *(volatile u32 *)(CONFIG_SYS_RAM_BASE |
(SDRAM_MODEREG_VALUE << LPC18XX_EMC_MODEREG_ADDR_SHIFT));
/*
* Normal mode
*/
LPC_EMC->dy_ctrl =
(LPC_EMC_DYCTRL_I_NORMAL << LPC_EMC_DYCTRL_I_BITS);
/*
* Enable DRAM buffer
*/
dy->cfg = (LPC18XX_EMC_AM << LPC_EMC_DYCFG_AM_BITS) |
LPC_EMC_DYCFG_B_MSK;
/*
* Fill in global info with description of DRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
#ifdef CONFIG_LCD
gd->fb_base = CONFIG_SYS_RAM_BASE + CONFIG_SYS_RAM_SIZE;
gd->fb_base = lcd_setmem(gd->fb_base);
#endif
return 0;
}
#ifdef CONFIG_LPC18XX_ETH
/*
* Register ethernet driver
*/
int board_eth_init(bd_t *bis)
{
return lpc18xx_eth_driver_init(bis);
}
#endif
#ifdef CONFIG_LCD
void lcd_enable(void)
{
/* Enable LCD clock */
/* FIXME replace these */
writel(0x09000800, 0x40050088);
#define CLK_RUN 1
#define CLK_AUTO 2
#define CLK_APB3_DAC_CFG 0x40051110
#define CLK_APB3_DAC_STAT 0x40051114
writel(CLK_RUN | CLK_AUTO, CLK_APB3_DAC_CFG);
while(!(readl(CLK_APB3_DAC_STAT) & CLK_RUN));
#define LPC_DAC_CR 0x400E1000
#define LPC_DAC_CR_VALUE(x) ((x & 0x3FF) << 6)
#define LPC_LCD_MAXIMUM_V 338
#define LPC_DAC_CTRL 0x400E1004
#define LPC_DAC_CTRL_DMA_ENA (1 << 3)
writel(LPC_DAC_CR_VALUE(0), LPC_DAC_CR);
writel(LPC_DAC_CTRL_DMA_ENA, LPC_DAC_CTRL);
/*
* Finally set value
*/
writel(LPC_DAC_CR_VALUE(LPC_LCD_MAXIMUM_V), LPC_DAC_CR);
}
struct clcd_config panel_info_clcd_priv = {
.address = (struct clcd_registers *) 0x40008000,
.tim0 = 0x01012874,
.tim1 = 0x0202250f,
.tim2 = 0x01df381e,
.tim3 = 0x00000000,
.cntl = 0x0000092b,
};
vidinfo_t panel_info = {
vl_col: 480,
vl_row: 272,
vl_bpix: 5,
priv: &panel_info_clcd_priv,
};
int overwrite_console(void)
{
return 1;
}
#endif
/*
* (C) Copyright 2012, 2013
*
* Alexander Potashev, Emcraft Systems, aspotas...@emcraft.com
* Pavel Boldin, Emcraft Systems, pabol...@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Configuration settings for the Infinisource LPC4357 board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Different revisions: Rev1 has 16 MB RAM, Rev2 has 32 MB RAM, Rev3 has 64 MB
RAM
*/
#define CONFIG_SYS_BOARD_REV 0x3
/*
* Disable debug messages
*/
//#define DEBUG
/*
* This is an ARM Cortex-M4 CPU core. Also use the common Cortex-M3 code.
*/
#define CONFIG_SYS_ARMCORTEXM3
#define CONFIG_SYS_ARMCORTEXM4
/*
* Enable RAMCODE to be loaded into separated section.
*/
#define CONFIG_ARMCORTEXM3_RAMCODE
#define CONFIG_MEM_RAMCODE_BASE 0x10000000
#define CONFIG_MEM_RAMCODE_LEN (32 * 1024)
/*
* This is the NXP LPC4357 device which is backward-compatible with LPC1850
*/
#define CONFIG_SYS_LPC18XX
/*
* Except it have eNVM
*/
#define CONFIG_LPC43XX_ENVM
/*
* Add header to the U-Boot image to pass necessary information
* to the Boot ROM bootloader.
*/
#undef CONFIG_LPC18XX_BOOTHEADER
/*
* Compute checksum
*/
#define CONFIG_LPC178X_FCG
/*
* Enable GPIO driver
*/
#define CONFIG_LPC18XX_GPIO
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#if (CONFIG_SYS_BOARD_REV == 1)
# define CONFIG_SYS_BOARD_REV_STR "1"
#elif (CONFIG_SYS_BOARD_REV == 2)
# define CONFIG_SYS_BOARD_REV_STR "2"
#elif (CONFIG_SYS_BOARD_REV == 3)
# define CONFIG_SYS_BOARD_REV_STR "3"
#else
# error "Unknown board rev"
#endif
/*
* Monitor prompt
*/
#define CONFIG_SYS_PROMPT "LPC4357> "
/*
* We want to call the CPU specific initialization
*/
#define CONFIG_ARCH_CPU_INIT
/*
* No flash
*/
#define CONFIG_SYS_NO_FLASH
/*
* We do not use cortex_m3_soc_init() yet.
*/
#undef CONFIG_ARMCORTEXM3_SOC_INIT
/*
* Clock configuration (see cpu/arm_cortexm3/lpc18xx/clock.c for details)
*/
/*
* This should be setup to the board specific rate for the external oscillator
*/
#define CONFIG_LPC18XX_EXTOSC_RATE 12000000
/*
* PLL1 multiplier value (1..256)
*/
#define CONFIG_LPC18XX_PLL1_M 17 /* 12 MHz * 17 = 204 MHz */
/*
* Number of clock ticks in 1 sec
*/
#define CONFIG_SYS_HZ 1000
/*
* Use internal clock (CPU clock) for the Cortex-M4 SysTick timer
*/
#define CONFIG_ARMCORTEXM3_SYSTICK_CPU
/*
* Enable/disable h/w watchdog
*/
#undef CONFIG_HW_WATCHDOG
/*
* No interrupts
*/
#undef CONFIG_USE_IRQ
/*
* Memory layout configuration
*/
/*
* No internal flash on the NXP LPC4350 MCU. Setting CONFIG_MEM_NVM_LEN to the
* size of the contiguous region of internal SRAM at address 0x10000000.
*/
#define CONFIG_MEM_NVM_BASE 0x1A000000
#define CONFIG_MEM_NVM_LEN (512 * 1024)
#define CONFIG_MEM_NVM_SECTORS 15
#define CONFIG_MEM_NVM2_BASE 0x1B000000
#define CONFIG_MEM_NVM2_LEN (512 * 1024)
#define CONFIG_MEM_NVM2_SECTORS 15
#define CONFIG_MEM_RAM_BASE 0x10080000
#define CONFIG_MEM_RAM_LEN (20 * 1024)
#define CONFIG_MEM_RAM_BUF_LEN (1 * 1024)
#define CONFIG_MEM_MALLOC_LEN (15 * 1024)
#define CONFIG_MEM_STACK_LEN (4 * 1024)
/*
* malloc() pool size
*/
#define CONFIG_SYS_MALLOC_LEN CONFIG_MEM_MALLOC_LEN
/*
* Configuration of the external DRAM memory
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_CS 0 /* 0 .. 3 */
#define CONFIG_SYS_RAM_BASE 0x28000000
#if (CONFIG_SYS_BOARD_REV == 1)
# define CONFIG_SYS_RAM_SIZE (16 * 1024 * 1024)
#elif (CONFIG_SYS_BOARD_REV == 2)
# define CONFIG_SYS_RAM_SIZE (32 * 1024 * 1024)
#elif (CONFIG_SYS_BOARD_REV == 3)
# define CONFIG_SYS_RAM_SIZE (64 * 1024 * 1024)
#else
# error "Unknown board rev"
#endif
/*
* Buffers for Ethernet DMA (cannot be in the internal System RAM)
*/
#define CONFIG_MEM_ETH_DMA_BUF_BASE 0x20000000 /* Region of SRAM */
/*
* Use the CPU_CLOCK/2 for EMC
*/
#define CONFIG_LPC18XX_EMC_HALFCPU
/*
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_ADDR 0
*/
/* Uncomment the following line to enable the SPIFI interface */
#define CONFIG_SPIFI
#ifdef CONFIG_SPIFI
# define CONFIG_SPIFI_BASE 0x14000000
# define CONFIG_SPIFI_SIZE (32*1024*1024)
# define CONFIG_SPIFILIB_IN_ENVM
# ifndef CONFIG_ENV_IS_IN_FLASH
# define CONFIG_ENV_IS_IN_SPIFI
# define CONFIG_ENV_SIZE (4 * 1024)
# define CONFIG_ENV_ADDR CONFIG_SPIFI_BASE
# define CONFIG_ENV_ADDR_REDUND (CONFIG_SPIFI_BASE + 0x10000)
# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
# define CONFIG_ENV_OVERWRITE 1
# endif /* !CONFIG_ENV_IS_IN_FLASH */
#endif /* CONFIG_SPIFI */
/*
* Serial console configuration
*/
#define CONFIG_SYS_NS16550 1
#undef CONFIG_NS16550_MIN_FUNCTIONS
#define CONFIG_SYS_NS16550_SERIAL 1
/*
* Registers are 32-bit. The negative value tells the ns16550 driver that
* registers should be post-padded with zeroes (because the CPU is in
* little-endian mode.)
*/
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
/*
* USART0 uses the BASE_UART0_CLK clock
*/
#define CONFIG_SYS_NS16550_CLK clock_get(CLOCK_UART0)
#define CONFIG_CONS_INDEX 1
#if 0
# define CONFIG_UART0_CLOCK_XTAL
# define CONFIG_SERIAL0_SPECIAL_BAUDRATE 0xC10006
#endif
/*
* USART0 registers base: 0x40081000
* UART1 registers base: 0x40082000
* USART2 registers base: 0x400C1000
* USART3 registers base: 0x400C2000
*/
#define CONFIG_SYS_NS16550_COM1 0x40081000
/*
* Pin configuration for UART
*/
#define CONFIG_LPC18XX_UART_TX_IO_GROUP 15 /* PF */
#define CONFIG_LPC18XX_UART_TX_IO_PIN 10 /* PF.10 = USART0 TXD */
#define CONFIG_LPC18XX_UART_TX_IO_FUNC 1
#define CONFIG_LPC18XX_UART_RX_IO_GROUP 15 /* PF */
#define CONFIG_LPC18XX_UART_RX_IO_PIN 11 /* PF.11 = USART0 RXD */
#define CONFIG_LPC18XX_UART_RX_IO_FUNC 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Ethernet configuration
*/
#define CONFIG_NET_MULTI
#define CONFIG_LPC18XX_ETH
#define CONFIG_LPC18XX_ETH_DIV_SEL 1 /* 100-150 MHz */
#define CONFIG_LPC18XX_ENET_USE_PHY_RMII
/*
* Ethernet RX buffers are malloced from the internal SRAM (more precisely,
* from CONFIG_SYS_MALLOC_LEN part of it). Each RX buffer has size of 1536B.
* So, keep this in mind when changing the value of the following config,
* which determines the number of ethernet RX buffers (number of frames which
* may be received without processing until overflow happens).
*/
#define CONFIG_SYS_RX_ETH_BUFFER 2
#define CONFIG_SYS_TX_ETH_BUFFER 2
/*
* Console I/O buffer size
*/
#define CONFIG_SYS_CBSIZE 256
/*
* Print buffer size
*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_RAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_RAM_BASE + \
CONFIG_SYS_RAM_SIZE)
/*
* Needed by "loadb"
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_RAM_BASE
/*
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* not RAM, but CONFIG_SYS_MONITOR_BASE must be defined.
*/
#define CONFIG_SYS_MONITOR_BASE 0x0
/*
* Monitor is not in flash. Needs to define this to prevent
* U-Boot from running flash_protect() on the monitor code.
*/
#define CONFIG_MONITOR_IS_IN_RAM 1
/*
* Enable all those monitor commands that are needed
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BOOTD
#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_ECHO
#undef CONFIG_CMD_EDITENV
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_ITEST
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_MISC
#define CONFIG_CMD_NET /* Obligatory for the Ethernet driver to build */
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG
#if defined(CONFIG_SPI_FLASH)
#define CONFIG_CMD_SF
#endif
#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_COLOR 0x0000FF
#define CONFIG_BMP_24BPP
#define CONFIG_VIDEO_AMBA
#define CONFIG_CMD_BMP
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
/*
* To save memory disable long help
*/
#undef CONFIG_SYS_LONGHELP
/*
* Max number of command args
*/
#define CONFIG_SYS_MAXARGS 16
/*
* Auto-boot sequence configuration
*/
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_HOSTNAME infinisource-lpc4357
#define CONFIG_BOOTARGS \
"lpc18xx_platform=infinisource-lpc4357 "\
"console=ttyS0,115200 panic=10"
#define CONFIG_BOOTCOMMAND "run flashboot"
/*
* This ensures that the board-specific misc_init_r() gets invoked.
*/
#define CONFIG_MISC_INIT_R
#define KERNEL1_FLASH_BASE 0x140A0000
#define KERNEL2_FLASH_BASE 0x146A0000
/*
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x28000000\0" \
"addip=setenv bootargs ${bootargs}
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off\0"
\
"ethaddr=C0:31:BC:88:78:93\0" \
"serverip=169.254.10.1\0" \
"ipaddr=169.254.10.10\0" \
"splashimage=14020000\0" \
"flashboot=run addip;bootm ${uImage_offset}\0" \
"image=infinisource.uImage\0" \
"image_uboot=u-boot.bin\0" \
"netboot=tftp ${image};run addip;bootm\0" \
"update=tftp ${image};" \
"cp.b ${loadaddr} ${uImage_offset} ${filesize}\0" \
"uboot_offset=1A000000\0" \
"update_uboot=tftp ${image_uboot};" \
"cptf ${uboot_offset} ${loadaddr} ${filesize}\0"
/*
* Linux kernel boot parameters configuration
*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#endif /* __CONFIG_H */
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