Reuti <[email protected]> writes:
> It's the physical ID which is changing for each socket. Magny-Cours
> just output doubles for "physical id" and "core id" entries. But the
> "apicid" and "initial apicid" are changing. But I don't know what's
> happening for Intel CPUs for these entries.
If it's interesting to compare with Magny-Cours, here's the lstopo
output for Westmere, first with hyperthreading (or whatever it's called
now) off, and then switched on:
# lstopo
Machine (47GB)
NUMANode #0 (phys=0 24GB) + Socket #0 + L3 #0 (12MB)
L2 #0 (256KB) + L1 #0 (32KB) + Core #0
PU #0 (phys=0)
PU #1 (phys=12)
L2 #1 (256KB) + L1 #1 (32KB) + Core #1
PU #2 (phys=1)
PU #3 (phys=13)
L2 #2 (256KB) + L1 #2 (32KB) + Core #2
PU #4 (phys=2)
PU #5 (phys=14)
L2 #3 (256KB) + L1 #3 (32KB) + Core #3
PU #6 (phys=3)
PU #7 (phys=15)
L2 #4 (256KB) + L1 #4 (32KB) + Core #4
PU #8 (phys=4)
PU #9 (phys=16)
L2 #5 (256KB) + L1 #5 (32KB) + Core #5
PU #10 (phys=5)
PU #11 (phys=17)
NUMANode #1 (phys=1 24GB) + Socket #1 + L3 #1 (12MB)
L2 #6 (256KB) + L1 #6 (32KB) + Core #6
PU #12 (phys=6)
PU #13 (phys=18)
L2 #7 (256KB) + L1 #7 (32KB) + Core #7
PU #14 (phys=7)
PU #15 (phys=19)
L2 #8 (256KB) + L1 #8 (32KB) + Core #8
PU #16 (phys=8)
PU #17 (phys=20)
L2 #9 (256KB) + L1 #9 (32KB) + Core #9
PU #18 (phys=9)
PU #19 (phys=21)
L2 #10 (256KB) + L1 #10 (32KB) + Core #10
PU #20 (phys=10)
PU #21 (phys=22)
L2 #11 (256KB) + L1 #11 (32KB) + Core #11
PU #22 (phys=11)
PU #23 (phys=23)
# service cpuoffline start
Maybe offlining hyperthreads
# lstopo
Machine (47GB)
NUMANode #0 (phys=0 24GB) + Socket #0 + L3 #0 (12MB)
L2 #0 (256KB) + L1 #0 (32KB) + Core #0 + PU #0 (phys=0)
L2 #1 (256KB) + L1 #1 (32KB) + Core #1 + PU #1 (phys=1)
L2 #2 (256KB) + L1 #2 (32KB) + Core #2 + PU #2 (phys=2)
L2 #3 (256KB) + L1 #3 (32KB) + Core #3 + PU #3 (phys=3)
L2 #4 (256KB) + L1 #4 (32KB) + Core #4 + PU #4 (phys=4)
L2 #5 (256KB) + L1 #5 (32KB) + Core #5 + PU #5 (phys=5)
NUMANode #1 (phys=1 24GB) + Socket #1 + L3 #1 (12MB)
L2 #6 (256KB) + L1 #6 (32KB) + Core #6 + PU #6 (phys=6)
L2 #7 (256KB) + L1 #7 (32KB) + Core #7 + PU #7 (phys=7)
L2 #8 (256KB) + L1 #8 (32KB) + Core #8 + PU #8 (phys=8)
L2 #9 (256KB) + L1 #9 (32KB) + Core #9 + PU #9 (phys=9)
L2 #10 (256KB) + L1 #10 (32KB) + Core #10 + PU #10 (phys=10)
L2 #11 (256KB) + L1 #11 (32KB) + Core #11 + PU #11 (phys=11)
#
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