I am developing a FIR filter that will eventually accepts complex taps
reprogrammable during runtime. As a first iteration, I want to verify it
works like the in-tree module with int_vector real taps. So I configure the
settings register in OOT module's .xml file to take int_vector taps but
running it returns:
RuntimeError: RuntimeError: not yet implemented: int_vector

I guess it's because the in-tree module's ettus.rfnoc_fir_cci() make
function supports int_vector whereas my rfnocmodtool generated make
function hf_chlizer.fir() does not.

So I changed my OOT module's .xml to use ettus.rfnoc_fir_cci() instead of
hf_chlizer.fir() and output shows both I and Q samples are filtered
identically by real taps.

But ettus.rfnoc_fir_cci() does not seem to support complex_vector taps. So
I must revert to hf_chlizer.fir() in which case I get:
RuntimeError: RuntimeError: Invalid block definition in
/home/switchlanez/rfnoc/share/uhd/rfnoc/blocks/fir.xml: RuntimeError: Found
invalid arguments for block fir.

Or I could hack hf_chlizer.fir(). I started this by replacing int vectors
with std::complex vectors everywhere FIR taps were referenced in the
in-tree module's C++ library but I stopped when it traced up to block.h
because that may affect other modules.

1) What's the best approach to implement a vector of complex taps
reprogrammable during runtime?

2) My verilog code assumes one complex tap is 32 bits (leftmost 16 bits for
I, rightmost 16 bits for Q) and formats complex samples the same (in-tree
module also handles complex sample this way). Will UHD automatically
convert complex floats incoming from the host to sc16 for the embedded
settings registers?

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