Hello Guowang: First, if you are woking on GNSS (it's just my guess, but that's where 10.23 MHz usually comes from), you usually DON'T need to use 10.23 MS/s (see GNSS-SDR and gps-sdr-sim source codes). So, you may want to think about that before proceeding further.
If you absolutely want to use 10.23 MS/s, then you can try resampling your data (either on your PC, on the FPGA, or both). It may require a pretty serious resampler, though (could be difficult to this in real-time). You can try altering the actual hardware clock of the board, but do not expect it to be a trivial task. Regards, Kyeong Su Shin ________________________________ 보낸 사람: guowang qiu via USRP-users <[email protected]> 대신 USRP-users <[email protected]> 보낸 날짜: 2020년 4월 28일 화요일 오전 3:52 받는 사람: [email protected] <[email protected]> 참조: Damon Qiu <[email protected]> 제목: [USRP-users] 10.23Msps Sample Rate Hi all, We are trying to get 10.23Msps or 20.46Msps sample rate with X310. Latest UHD driver enables USRP x310 support 184.32MHz to 200MHz master clock rate. But it just support some discrete values，unfortunately, it just didn't support 10.23M*18 or 10.23M*19. We have tried to input an external reference clock of 10.23MHz, and we want to cheat x310 that the external clock is 10MHz. We set the master clock rate of the system as 200MHz. If the PLL can lock to the external clock source, the actual master clock rate is 10.23 × 20MHz. However, when the program is running, the UHD driver throws an exception, indicating: terminate called after throwing an instance of 'uhd::runtime_error' what(): RuntimeError: Reference Clock PLL failed to lock to external source. Is there any way to obtain 10.23Msps sample rate with X310? Best regards, Damon
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