Hello Damon, That does not mean that you have to use a physical 10.23 MHz clock. A good digital resampler should allow the device to transmit essentially the same signal. Implementing a good resampler could be challenging (a rational-resampler may take too much taps to implement), but there are still some feasible designs (especially if it does not need to process the data in real-time, by any chance, or if you are okay with writing HDL codes).
In fact, USRPs already do this. Their Rx chains sample at a faster rate, and then decimate the sampled data to the target sampling rates. Their Tx chains do the opposite. When you ask USRPs to sample at, say, 10 MS/s, their ADCs are not sampling at 10 MS/s: they sample at 200 MS/s, then provide you resampled version of the data at 10 MS/s. It's just that the default resamplers included in their FPGAs have limited capabilities, so they cannot cover the sampling rates that you are looking for. Also, I do not know what applications you are working on, but if you are working on GNSS (it's just my guess, since 10.23 MHz is a common rate for GNSS satellites), the precision of the data stream does not actually matter that much. Yes, you do want to use a good clock, so as the signals would correlate well, but you can make rough estimates (like using square shaping filter) when you are generating the data, and still get decent correlation peaks, as long as the assumptions are not bad enough to significantly break the correlation properties of the signals. This is regularly exploited in GNSS receivers and transmitters. If you still believe that you want to use a physical 10.23 MHz clock, then maybe you want to check out the fact that USRP x300s support 30.72 MHz external ref clock ( https://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_x3x0_hw_ref10M ). Maybe you can try inputting something like 30.69 MHz (10.23 * 3) as your ext ref clock.. but I am not so sure about this. (It WILL screw up some timing, but how bad?) Please note that you may need to use a recent version of the UHD and the FPGA firmware. Regards, Kyeong Su Shin ________________________________ 보낸 사람: guowang qiu <[email protected]> 보낸 날짜: 2020년 4월 29일 수요일 오전 3:13 받는 사람: Kyeong Su Shin <[email protected]> 참조: [email protected] <[email protected]>; Damon Qiu <[email protected]> 제목: Re: [USRP-users] 10.23Msps Sample Rate Hi Kyeong Su Shin, Thank you for your reply. We need to send out signal at a very precise time. Interval between packet transmitting needs to be an integral multiple of 1 / 10.23M, so the master clock rate is should be N*10.23MHz. Best regards, Damon On Tue, 28 Apr 2020 at 12:45, Kyeong Su Shin <[email protected]<mailto:[email protected]>> wrote: Hello Guowang: First, if you are woking on GNSS (it's just my guess, but that's where 10.23 MHz usually comes from), you usually DON'T need to use 10.23 MS/s (see GNSS-SDR and gps-sdr-sim source codes). So, you may want to think about that before proceeding further. If you absolutely want to use 10.23 MS/s, then you can try resampling your data (either on your PC, on the FPGA, or both). It may require a pretty serious resampler, though (could be difficult to this in real-time). You can try altering the actual hardware clock of the board, but do not expect it to be a trivial task. Regards, Kyeong Su Shin ________________________________ 보낸 사람: guowang qiu via USRP-users <[email protected]<mailto:[email protected]>> 대신 USRP-users <[email protected]<mailto:[email protected]>> 보낸 날짜: 2020년 4월 28일 화요일 오전 3:52 받는 사람: [email protected]<mailto:[email protected]> <[email protected]<mailto:[email protected]>> 참조: Damon Qiu <[email protected]<mailto:[email protected]>> 제목: [USRP-users] 10.23Msps Sample Rate Hi all, We are trying to get 10.23Msps or 20.46Msps sample rate with X310. Latest UHD driver enables USRP x310 support 184.32MHz to 200MHz master clock rate. But it just support some discrete values，unfortunately, it just didn't support 10.23M*18 or 10.23M*19. We have tried to input an external reference clock of 10.23MHz, and we want to cheat x310 that the external clock is 10MHz. We set the master clock rate of the system as 200MHz. If the PLL can lock to the external clock source, the actual master clock rate is 10.23 × 20MHz. However, when the program is running, the UHD driver throws an exception, indicating: terminate called after throwing an instance of 'uhd::runtime_error' what(): RuntimeError: Reference Clock PLL failed to lock to external source. Is there any way to obtain 10.23Msps sample rate with X310? Best regards, Damon
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