Dear All, I have a question about the control of the TX/RX DSAs on the N310 platform.
I have a specific line-up for the RX and TX chains and I'd like to set specific values to the TX and RX DSAs that are on the N310's daughter board card. Are the control lines for the DSA's hooked up to SW for control via UHD/MPM? From what I can tell, this is not a SW enabled feature on the N310. Looking through the FPGA code, the DSAs are hooked up to the dsa_tx<1,2>_<a,b>_out_iob buffers. I've traced these lines as follows: IO buffer => db_gpio_out wire in top module n3xx => n3xx_core => db_fe_core => db_control => db_gpio_atr (gpio_atr module). Inside the gpio_atr verilog module, there are some registers related to the ATR logic but not DSAs. There is logic to control the db_gpio via a gpio_out_fab signal line, but I trace this signal and it goes back up to the top level n3xx module as an unconnected wire. Is there a connection that I am missing? Thank you, Colby
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