On 06/18/2020 06:28 PM, Colby Boyer wrote:
Hi Marcus,
Thank you for your response and pointing me in the right direction.
Yes, I see that flow now after tracing through UHD to a poke32
interface for twiddling the bits. Before I was mostly looking at the
Verilog FPGA code and how the registers were being mapped was not that
clear. It looks like the ATR idle register is being repurposed to
control the TX and RX DSAs.
It seems that the DSA command is put out over the wire via the CHDR
interface with the following path for the N310. Host -> 10 GigE ->
N310 10GigE Switch -> RFNoC -> radio core. It does not interact with
MPM running on Linux, is that correct?
Looking at the gain control for the AD9371, this looks to be
translated to an RPC call and sent to MPM that calls the mykonos
API/SPI transaction. Does that sound about correct?
Thanks
Colby
It was my impression that in an MPM-based system, ALL the
control-traffic goes through MPM. I could be wrong, as I haven't
studied that code
extensively.
I'll see if I can get anyone from R&D to comment.
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