On 06/17/2020 02:31 PM, Colby Boyer via USRP-users wrote:
Dear All,
I have a question about the control of the TX/RX DSAs on the N310
platform.
I have a specific line-up for the RX and TX chains and I'd like to set
specific values to the TX and RX DSAs that are on the N310's daughter
board card. Are the control lines for the DSA's hooked up to SW for
control via UHD/MPM? From what I can tell, this is not a SW enabled
feature on the N310.
Looking through the FPGA code, the DSAs are hooked up to the
dsa_tx<1,2>_<a,b>_out_iob buffers. I've traced these lines as follows:
IO buffer => db_gpio_out wire in top module n3xx => n3xx_core =>
db_fe_core => db_control => db_gpio_atr (gpio_atr module).
Inside the gpio_atr verilog module, there are some registers related
to the ATR logic but not DSAs. There is logic to control the db_gpio
via a gpio_out_fab signal line, but I trace this signal and it goes
back up to the top level n3xx module as an unconnected wire.
Is there a connection that I am missing?
Thank you,
Colby
Took me a while to find the schematic for the N3XX daughtercard.
The DSAs are made by Peregrine (PE43704 in the RX direction, PE42553 in
the TX direction).
I'd be surprised if these weren't actually supported in UHD. If you use
the "get_gain_names" API call:
https://www.gnuradio.org/doc/doxygen/classgr_1_1uhd_1_1usrp__block.html#a756c14c66c5d9530f69e99afd6a4bb2d
You can see which individual gain-control elements are available to the
UHD, and then you can use a specific one of those gain-control elements
in a "set_gain" call:
https://www.gnuradio.org/doc/doxygen/classgr_1_1uhd_1_1usrp__block.html#a81ee1048dbd04c8664f1ea95129203f4
Using the 2nd form of the call that takes a gain name. Without using a
gain name, UHD will distribute gain settings over the gain-setting
elements that are available to it, typically optimizing for noise
figure in those settings.
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