Following the gain block tutorial from GRCON20, when I read from the registers
using gain_block->regs().peek32(0x0), the default value that is return is not
the same as set during reset. The default value I read is always 0 even when my
verilog sets it to some other value after rebuilding the image.
Has anyone seen this behavior?
Also i am having problems with other FPGA builds involving the registers to
please tell me if something is wrong with rfnoc 4.0 controlport.
All i've done is taken the default gain block and added another default value
after reset:
localparam REG_USER_ADDR = 0; // Address for example user register
localparam REG_USER_DEFAULT = 1; // Default value for user register
localparam REG_USER_DEFAULT2 = 2; //Default value for user register after
reset
reg [31:0] reg_user = REG_USER_DEFAULT;
always @(posedge ctrlport_clk) begin
if (ctrlport_rst) begin
reg_user = REG_USER_DEFAULT2;
end else begin
// Default assignment
m_ctrlport_resp_ack <= 0;
// Read user register
if (m_ctrlport_req_rd) begin // Read request
case (m_ctrlport_req_addr)
REG_USER_ADDR: begin
m_ctrlport_resp_ack <= 1;
m_ctrlport_resp_data <= reg_user;
end
endcase
end
// Write user register
if (m_ctrlport_req_wr) begin // Write requst
case (m_ctrlport_req_addr)
REG_USER_ADDR: begin
m_ctrlport_resp_ack <= 1;
reg_user <= m_ctrlport_req_data[31:0];
end
endcase
end
end
end
Jeff
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