Something must be different between your code and the example. Did you modify anything in the block's YAML and regenerate the noc_shell for your block? Maybe something was changed in that process. Perhaps you could post the code for your block (specifically the HDL and YAML)?
Wade On Mon, Sep 20, 2021 at 4:21 PM Hodges, Jeff <[email protected]> wrote: > The reset value being stuck at 0 may not be a significant issue but it is > one of two issues I am having and the easiest to debug. > > > The other issue is that if the addr 0 is not writeable, then the control > port will not read/write from any of the registers. All of it simulates > fine but after building and testing, I get ACK timeouts on the controlport > bus. > > > > Jeff > > > > *From:* Hodges, Jeff via USRP-users <[email protected]> > *Sent:* Monday, September 20, 2021 3:09 PM > *To:* Wade Fife <[email protected]>; Rob Kossler <[email protected]> > *Cc:* [email protected] > *Subject:* [USRP-users] Re: rfnoc 4.0 gain block tutorial --> register > problem > > > > Rob/Wade, > > > > Thank you for the feedback. I have been running the testbenches and they > succeed but when I build the code the default value is still 0. > > > > I went back and copied the two files: rfnoc_block_gain.v and > rfnoc_block_gain_tb.sv to the OOT module, replacing the gain code I had, > and reran the testbench and rebuilt the image and the default value of > register address 0x0 is still 0. > > > > Any thoughts on what else could be wrong? > > > > Jeff > > > > *From:* Wade Fife <[email protected]> > *Sent:* Tuesday, September 14, 2021 3:25 PM > *To:* Rob Kossler <[email protected]> > *Cc:* Hodges, Jeff <[email protected]>; > [email protected] > *Subject:* Re: [USRP-users] Re: rfnoc 4.0 gain block tutorial --> > register problem > > > > Hi Jeff, > > > > I agree with Rob that "=" should be "<=" but I don't think that's causing > any harm here. I copied and pasted your code into the gain example and > tested it, and it seems to work as I expected. So there's probably > something wrong that's unrelated to that code snippet. Take a look at the > gain example to see what's different in yours. I would also suggest > simulating your code rather than resorting to chipscope. You can use the > example gain testbench as a starting point. > > > > > https://github.com/EttusResearch/uhd/blob/master/host/examples/rfnoc-example/fpga/rfnoc_block_gain/rfnoc_block_gain.v > > > https://github.com/EttusResearch/uhd/blob/master/host/examples/rfnoc-example/fpga/rfnoc_block_gain/rfnoc_block_gain_tb.sv > > > > The reset should be asserted when the graph is first initialized, so you > should not be able to read the initial value of the register > (REG_USER_DEFAULT), only the reset value (REG_USER_DEFAULT2). If that reset > isn't happening then perhaps there's something wrong with the reset > connection or the clock connection. Also, it's usually good practice to > make the reset and initial value the same. Some FPGAs don't really support > them being different, although I think this is supported on Xilinx 7 Series. > > > > Thanks, > > > > Wade > > > > On Mon, Sep 13, 2021 at 3:03 PM Rob Kossler <[email protected]> wrote: > > Hi Jeff, > > I am mostly a novice at FPGA development, but I have created a few blocks > in rfnoc 4.0 with multiple registers and they seem to behave properly. One > thing I noticed in your original post below is that when you assign the > value REG_USER_DEFAULT2, you use "=" rather than "<=". It seems it should > be the latter. I don't really know what issues, if any, this would cause. > > Rob > > > > On Mon, Sep 13, 2021 at 1:07 PM Hodges, Jeff via USRP-users < > [email protected]> wrote: > > I'm now convinced there is something majorly wrong with UHD4.0 > controlport. Not only am I experiencing the issue I have described here > but if I create an image with two write registers (0x0 and 0x4) it works, > but if I create two write registers addresses of 0x4 and 0x8, it fails both > read and write. > > > Is anyone using this UHD4.0? I never had these problems with UHD3.15. I'm > building for the X310. > > > > I can try to debug with chipscope but that is a pain and would rather not > do waste time if someone else has already identified the source of this > problem. > > > > Thanks, > > > > Jeff > ------------------------------ > > *From:* Hodges, Jeff via USRP-users <[email protected]> > *Sent:* Monday, September 13, 2021 11:48:06 AM > *To:* [email protected] > *Subject:* [USRP-users] Re: rfnoc 4.0 gain block tutorial --> register > problem > > > > I can read and write from register addr 0x0 but the default value read > from peek32(0x0) is 0 regardless of what I set the REG_USER_DEFAULT value > to. > > > > This only occurs on register addr 0x0. > > > > Jeff > > > ------------------------------ > > *From:* Hodges, Jeff via USRP-users <[email protected]> > *Sent:* Saturday, September 11, 2021 5:02 PM > *To:* [email protected] > *Subject:* [USRP-users] rfnoc 4.0 gain block tutorial --> register problem > > > > Following the gain block tutorial from GRCON20, when I read from the > registers using gain_block->regs().peek32(0x0), the default value that is > return is not the same as set during reset. The default value I read is > always 0 even when my verilog sets it to some other value after rebuilding > the image. > > > > Has anyone seen this behavior? > > > > Also i am having problems with other FPGA builds involving the registers > to please tell me if something is wrong with rfnoc 4.0 controlport. > > All i've done is taken the default gain block and added another default > value after reset: > > > > > > localparam REG_USER_ADDR = 0; // Address for example user register > localparam REG_USER_DEFAULT = 1; // Default value for user register > localparam REG_USER_DEFAULT2 = 2; //Default value for user register > after reset > > reg [31:0] reg_user = REG_USER_DEFAULT; > > always @(posedge ctrlport_clk) begin > if (ctrlport_rst) begin > reg_user = REG_USER_DEFAULT2; > end else begin > // Default assignment > m_ctrlport_resp_ack <= 0; > > // Read user register > if (m_ctrlport_req_rd) begin // Read request > case (m_ctrlport_req_addr) > REG_USER_ADDR: begin > m_ctrlport_resp_ack <= 1; > m_ctrlport_resp_data <= reg_user; > end > endcase > end > > // Write user register > if (m_ctrlport_req_wr) begin // Write requst > case (m_ctrlport_req_addr) > REG_USER_ADDR: begin > m_ctrlport_resp_ack <= 1; > reg_user <= m_ctrlport_req_data[31:0]; > end > endcase > end > end > end > > > > Jeff > > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] > > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] > >
_______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
