Hi Jeff, I am mostly a novice at FPGA development, but I have created a few blocks in rfnoc 4.0 with multiple registers and they seem to behave properly. One thing I noticed in your original post below is that when you assign the value REG_USER_DEFAULT2, you use "=" rather than "<=". It seems it should be the latter. I don't really know what issues, if any, this would cause. Rob
On Mon, Sep 13, 2021 at 1:07 PM Hodges, Jeff via USRP-users < [email protected]> wrote: > I'm now convinced there is something majorly wrong with UHD4.0 > controlport. Not only am I experiencing the issue I have described here > but if I create an image with two write registers (0x0 and 0x4) it works, > but if I create two write registers addresses of 0x4 and 0x8, it fails both > read and write. > > > Is anyone using this UHD4.0? I never had these problems with UHD3.15. I'm > building for the X310. > > > I can try to debug with chipscope but that is a pain and would rather not > do waste time if someone else has already identified the source of this > problem. > > > Thanks, > > > Jeff > ------------------------------ > *From:* Hodges, Jeff via USRP-users <[email protected]> > *Sent:* Monday, September 13, 2021 11:48:06 AM > *To:* [email protected] > *Subject:* [USRP-users] Re: rfnoc 4.0 gain block tutorial --> register > problem > > > I can read and write from register addr 0x0 but the default value read > from peek32(0x0) is 0 regardless of what I set the REG_USER_DEFAULT value > to. > > > This only occurs on register addr 0x0. > > > Jeff > > > ------------------------------ > *From:* Hodges, Jeff via USRP-users <[email protected]> > *Sent:* Saturday, September 11, 2021 5:02 PM > *To:* [email protected] > *Subject:* [USRP-users] rfnoc 4.0 gain block tutorial --> register problem > > > Following the gain block tutorial from GRCON20, when I read from the > registers using gain_block->regs().peek32(0x0), the default value that is > return is not the same as set during reset. The default value I read is > always 0 even when my verilog sets it to some other value after rebuilding > the image. > > > Has anyone seen this behavior? > > > Also i am having problems with other FPGA builds involving the registers > to please tell me if something is wrong with rfnoc 4.0 controlport. > > All i've done is taken the default gain block and added another default > value after reset: > > > > localparam REG_USER_ADDR = 0; // Address for example user register > localparam REG_USER_DEFAULT = 1; // Default value for user register > localparam REG_USER_DEFAULT2 = 2; //Default value for user register > after reset > > reg [31:0] reg_user = REG_USER_DEFAULT; > > always @(posedge ctrlport_clk) begin > if (ctrlport_rst) begin > reg_user = REG_USER_DEFAULT2; > end else begin > // Default assignment > m_ctrlport_resp_ack <= 0; > > // Read user register > if (m_ctrlport_req_rd) begin // Read request > case (m_ctrlport_req_addr) > REG_USER_ADDR: begin > m_ctrlport_resp_ack <= 1; > m_ctrlport_resp_data <= reg_user; > end > endcase > end > > // Write user register > if (m_ctrlport_req_wr) begin // Write requst > case (m_ctrlport_req_addr) > REG_USER_ADDR: begin > m_ctrlport_resp_ack <= 1; > reg_user <= m_ctrlport_req_data[31:0]; > end > endcase > end > end > end > > > Jeff > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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