On 2022-05-18 16:28, Brian Padalino wrote:
I believe this is a slightly different issue. The previous issue was
the LVDS interface is already used, but the faster 61.44 Msps was not
supported for dual channel operations. The FPGA used is a Zynq device
on the E320.
Thanks for having a better memory :)
The interface here is CMOS and talking to a Spartan 6 device with a
bank voltage of 1.8v. This inherently makes it impossible to program
the FPGA for those pins to utilize LVDS.
Thanks, I only "play hardware guy" in very limited contexts. Yeah, it
looks like 2.5V (or hair lower) is the lowest common-mode voltage
supported by LVDS.
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