Hello, There might be some changes needed in the source code. I’m not sure what exactly (maybe prc_clock_map should be changed), but it seems the configuration for 100MHz clock multiply (3e9 sample rate) is still present in x4xx_sample_pll.py and x4xx_reference_pll.py.
I can try build 100MHz version for you if you need it and if you are not afraid to modify slightly UHD code to find out what exactly might be missing to enable 100MHz support again. Best Regards,\ Piotr Krysik
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