Hi Wade,
thank you very much! That indeed did the trick.

Dario Pennisi

On Fri, Nov 25, 2022 at 6:21 PM Wade Fife <[email protected]> wrote:

> Hi Dario,
>
> It looks like this mode was never officially supported. I'm going to
> follow up with R&D on Monday (it's a holiday in the US), since I don't know
> if there's a reason this mode wasn't kept in the code. The recommended way
> to get 125 Msps is to use X4_200 with the DDC and a master clock rate of
> 250e6. But it sounds like you need 125 Msps coming out of the radio.
>
> To get it to work the way you want, I think you just need to update the
> master_to_sample_clk dict as Piotr mentioned.
>
>
> https://github.com/EttusResearch/uhd/blob/321295fba49fb66ede365afbd9ef62971cdfbfca/mpm/python/usrp_mpm/periph_manager/x4xx_rfdc_ctrl.py#L54
>
> Add an entry to the table with:
>
> 125e6*1:       (3.00000e9, 8, False, False), # RF (1M-8G)
>
> Note that this file is part of MPM, so you actually need to edit this file
> on the X410 then restart it for it to take effect. This is where the file
> is on my X410:
>
> /usr/lib/python3.7/site-packages/usrp_mpm/periph_manager/x4xx_rfdc_ctrl.py
>
> After restarting the X410, you should be able to set the master_clock_rate
> to 125e6 as Marcus mentioned. If possible, I'll see if I can get this added
> to UHD so it will be available in the future.
>
> Thanks,
>
> Wade
>
> On Fri, Nov 25, 2022 at 9:32 AM Marcus D. Leech <[email protected]>
> wrote:
>
>> On 25/11/2022 06:20, Dario Pennisi wrote:
>>
>> Hi Piotr,
>> thank you very much. i'll look into it. unfortunately it worked at 125
>> MHz on UHD 4.0 when most of the stuff was hardcoded... anyway I'll figure
>> out.
>>
>> Dario Pennisi
>>
>> I'll note that UHD support for X410 wasn't *official* until UHD 4.1, so
>> anything that's based on 4.0 is based on code
>>   that was nearly-guaranteed to be "fluid".
>>
>>
>>
>> On Fri, Nov 25, 2022 at 10:51 AM <[email protected]> wrote:
>>
>>> Hello,
>>>
>>> I recently experimented with adding new master clock definitions for
>>> X411 (my port of X410 code to ZCU111).
>>>
>>> Here is a commit that does that:
>>>
>>>
>>> https://github.com/ptrkrysik/uhd/commit/719257702b788703e24fa8595d190c70114f5011
>>>
>>> But the clocking chips on ZCU111 are different so from you perspective
>>> the commit might be cluttered with useless stuff.
>>>
>>> From my experience the key are ‘master_to_sample_clk‘ dict from
>>> x4xx_rfdc_ctrl.py
>>> <https://github.com/ptrkrysik/uhd/commit/719257702b788703e24fa8595d190c70114f5011#diff-512da83981e88a61c70b093f36b15628ec086f429613f79abc25234548a6cfdc>
>>> (currently there is no master clock rate of 125MS/s or 100MS/s,
>>> there is 2*125MS/s or 200MS/s) and ‘prc_clock_map from’
>>> zcu111_clk_mgr.py
>>> <https://github.com/ptrkrysik/uhd/commit/719257702b788703e24fa8595d190c70114f5011#diff-d91773ec3db6663fcee00c00022faff9981ec5902f6ae807f09f9519903fe276>.
>>> Maybe legacy mode (is_legacy_mode) is also relevant in your case.
>>> I don’t what it was for exactly - I just removed it from X411 specific
>>> code as I don’t have any ‘legacy’ stuff that I need to support.
>>>
>>> Then you need to verify if ‘config‘ function in x4xx_sample_pll.py (and
>>> maybe x4xx_reference_pll.py) contains everything that it should for
>>> your needs. After short look it seems that it has what is needed as it
>>> has definition of 100MHz VCXO for 3e9 sample clock.
>>>
>>> If this used to work once, and you know when it worked, then you task is
>>> simpler - you need to look for changes in the mentioned files and especially
>>> in the structures that I pointed to.
>>>
>>> Best Regards,
>>> Piotr Krysik
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>>>
>>
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