Hi Piotr, thank you very much. i'll look into it. unfortunately it worked at 125 MHz on UHD 4.0 when most of the stuff was hardcoded... anyway I'll figure out.
Dario Pennisi On Fri, Nov 25, 2022 at 10:51 AM <[email protected]> wrote: > Hello, > > I recently experimented with adding new master clock definitions for X411 > (my port of X410 code to ZCU111). > > Here is a commit that does that: > > > https://github.com/ptrkrysik/uhd/commit/719257702b788703e24fa8595d190c70114f5011 > > But the clocking chips on ZCU111 are different so from you perspective the > commit might be cluttered with useless stuff. > > From my experience the key are ‘master_to_sample_clk‘ dict from > x4xx_rfdc_ctrl.py > <https://github.com/ptrkrysik/uhd/commit/719257702b788703e24fa8595d190c70114f5011#diff-512da83981e88a61c70b093f36b15628ec086f429613f79abc25234548a6cfdc> > (currently there is no master clock rate of 125MS/s or 100MS/s, > there is 2*125MS/s or 200MS/s) and ‘prc_clock_map from’ zcu111_clk_mgr.py > <https://github.com/ptrkrysik/uhd/commit/719257702b788703e24fa8595d190c70114f5011#diff-d91773ec3db6663fcee00c00022faff9981ec5902f6ae807f09f9519903fe276>. > Maybe legacy mode (is_legacy_mode) is also relevant in your case. > I don’t what it was for exactly - I just removed it from X411 specific > code as I don’t have any ‘legacy’ stuff that I need to support. > > Then you need to verify if ‘config‘ function in x4xx_sample_pll.py (and > maybe x4xx_reference_pll.py) contains everything that it should for > your needs. After short look it seems that it has what is needed as it has > definition of 100MHz VCXO for 3e9 sample clock. > > If this used to work once, and you know when it worked, then you task is > simpler - you need to look for changes in the mentioned files and especially > in the structures that I pointed to. > > Best Regards, > Piotr Krysik > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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