On Tue, May 13, 2025 at 4:34 AM sp <stackprogra...@gmail.com> wrote:
> In RFNOC block i need set sps a muliplay of master clock but not need high > sps. I need low sps but I want to not use any ddc block in my usrp fpga > image? Is it possible ? Can anyone guide me? Thanks in advance > No. The radio sample rates are fixed to the master clock rate. Any type of sample rate conversion needs to be done digitally. This is typically done with the DUC or DDC. You could write your own block to do it if you wanted, but it needs to just do the same thing the DUC or DDC does. Why can't you use the DDC in your design? Brian
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