-------- In message <[email protected]>, Attila Kinali writes:
>2) If I look at the documentation of the HP3458, they reach 28bits at >166ms integration time. Yet the HP Journal article talks about 100nV/√Hz >input noise. Ie the noise of the HP3458 is over a factor 5 higher, yet the >ENOB @100ms is 2 bits better. It barely matches up, when I ignore the >low frequency noise, but the factor of 5 in noise (or 2.3 bits) difference >remains. Where does this discrepancy come from? I am not sure why you call your circuit a "multi-slope ADC", I can only see one pair of current sources ? HP3458 uses six different slopes (Fig 8/p. 12) in a deviously smart asymmetric layout: [+1024,+256,+16,+1,-4,-64,-256,-1024] The trick to multislope is that it can cut down the convergence time, and that in turn reduces the effect of all the drift/leakage error sources proportionally. I suspect you also significantly underestimate the "non-ideal component" source of errors. The trick in Fig 7/p.12 is much more important than most people realize and HP's implementation is significantly more interesting than Fig 7 lets on, because it involves 8 switches instead of two. If you want to have any dream of getting performance like HP3458, you will have to write a lot of code to do the same "auto"-calibrations as the HP3458, and you will have to run it on a regular basis to cope with component drift. There is no free lunches after bit 20... -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 [email protected] | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. _______________________________________________ volt-nuts mailing list -- [email protected] To unsubscribe, go to http://lists.febo.com/mailman/listinfo/volt-nuts_lists.febo.com and follow the instructions there.
