Hi Julien,
> On 19 Jun 2023, at 19:01, Julien Grall <jul...@xen.org> wrote:
>
> From: Julien Grall <jgr...@amazon.com>
>
> On older version of the Arm Arm (ARM DDI 0487E.a, B2-125) there were
> the following paragraph:
>
> "DMB and DSB instructions affect reads and writes to the memory system
> generated by Load/Store instructions and data or unified cache
> maintenance instructions being executed by the PE. Instruction fetches
> or accesses caused by a hardware translation table access are not
> explicit accesses."
>
> Newer revision (e.g. ARM DDI 0487J.a) doesn't have the second sentence
> (it might be somewhere else in the Arm Arm). But the interpretation is
> not much different.
>
> In setup_fixmap(), we write the fixmap area and may be used soon after,
> for instance, to write to the UART. IOW, there could be hardware
> translation table access. So we need to ensure the 'dsb' has completed
> before continuing. Therefore add an 'isb'.
>
> Fixes: 2b11c3646105 ("xen/arm64: head: Remove 1:1 mapping as soon as it is
> not used")
> Signed-off-by: Julien Grall <jgr...@amazon.com>
Reviewed-by: Bertrand Marquis <bertrand.marq...@arm.com>
Cheers
Bertrand
> ---
> xen/arch/arm/arm64/head.S | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> index f37133cf7ccd..4ea64e70997b 100644
> --- a/xen/arch/arm/arm64/head.S
> +++ b/xen/arch/arm/arm64/head.S
> @@ -769,6 +769,11 @@ setup_fixmap:
> create_table_entry boot_second, xen_fixmap, x0, 2, x1, x2, x3
> /* Ensure any page table updates made above have occurred. */
> dsb nshst
> + /*
> + * The fixmap area will be used soon after. So ensure no hardware
> + * translation happens before the dsb completes.
> + */
> + isb
>
> ret
> ENDPROC(setup_fixmap)
> --
> 2.40.1
>
