> On 19 Jun 2023, at 18:01, Julien Grall <jul...@xen.org> wrote:
> 
> From: Julien Grall <jgr...@amazon.com>
> 
> On older version of the Arm Arm (ARM DDI 0487E.a, B2-125) there were
> the following paragraph:
> 
> "DMB and DSB instructions affect reads and writes to the memory system
> generated by Load/Store instructions and data or unified cache
> maintenance instructions being executed by the PE. Instruction fetches
> or accesses caused by a hardware translation table access are not
> explicit accesses."
> 
> Newer revision (e.g. ARM DDI 0487J.a) doesn't have the second sentence
> (it might be somewhere else in the Arm Arm). But the interpretation is
> not much different.
> 
> In setup_fixmap(), we write the fixmap area and may be used soon after,
> for instance, to write to the UART. IOW, there could be hardware
> translation table access. So we need to ensure the 'dsb' has completed
> before continuing. Therefore add an 'isb'.
> 
> Fixes: 2b11c3646105 ("xen/arm64: head: Remove 1:1 mapping as soon as it is 
> not used")
> Signed-off-by: Julien Grall <jgr...@amazon.com>

Reviewed-by: Luca Fancellu <luca.fance...@arm.com>



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