On 20/03/07, Gilles Chanteperdrix <[EMAIL PROTECTED]> wrote:
Muruganandam Ganapathy wrote:
 > The board is based on the Fujitsu SOC which has the ARM926EJ processor
core.
 >
 > This board has SPI, I2C and 10/100 ethernet interfaces and it can
support
 > 16/32MB SDRAM
 > and 4/8MB flash memory.

You still do not tell us the name of the board, but it is probably not
supported.

 >
 >
 > In addition, I would like to know the interrupt reponse  mesaured with
 > Xenomai in ARM9
 > processor based platforms, if any.
 > The interrupt response expected is around 40 -50 microseconds in our
case.
 > The interrupt response I mean, it is the time between the generation of
the
 > interrupt and the actual ISR invocation.
 >
 >
 > Whether use of Xenomai will enable us meet this timing reqirement.

The latencies I have observed so far on ARM are usually larger than 150
microseconds, but these are userspace dispatch latencies.

So, you could improve situation if you stay in interrupt handlers.

Another way to improve the situation a bit more is to use ucLinux, if
your platform is supported.

Still, IMHO, 40-50 microseconds is too ambitious.

Gilles, as I understood the question was about the interrupt latency, not
the scheduling one.

I guess, the vitually tagged cache is an additional component of high
scheduling latencies on ARM.

The interrupt latency should be ok though.


--


                                            Gilles Chanteperdrix.

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--
Best regards,
Dmitry Adamushko
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