Jan Kiszka wrote:
> Gilles Chanteperdrix wrote:
>>Jan Kiszka wrote:
>>>I think implementing coloured caches (with reservations for RT
>>>processes) could be an option as well. Once RT context switches no
>>>longer require full cache flushes, those for non-RT processes could be
>>>made interruptible. But all this would require heavy Linux hacking, I'm
>>Using TCM removes any cache effect and does not require Linux hacking.
> How is TCM managed? Can you push parts of I-pipe/Xenomai or even some
> applications into it? Or does this only help here if you have a few ops
> of an interrupt handler to be saved from the (RT-wise) lousy caching
> architecture of ARM?
TCM are 2 16K contiguous memory areas: one where data can be put, the
other where code can be put. They are mapped into the address space, and
once it is done, some data or code must be copied into them. Moving one
function to the TCM should be pretty straight-forward, allowing several
arbitrary functions to be in the TCM would probably require some more
work: a possible implementation would be to put the functions and data
in some specific sections that would be copied in the TCM at load time.
> [I threw coloured caches into the ring also to trigger some discussion
> on a long-term solution for MMU-based Xenomai on ARM.]
Right, TCM do not exist on all ARM.
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