Gilles Chanteperdrix wrote: > Jan Kiszka wrote: >> I think implementing coloured caches (with reservations for RT >> processes) could be an option as well. Once RT context switches no >> longer require full cache flushes, those for non-RT processes could be >> made interruptible. But all this would require heavy Linux hacking, I'm >> afraid. > > Using TCM removes any cache effect and does not require Linux hacking. >
How is TCM managed? Can you push parts of I-pipe/Xenomai or even some applications into it? Or does this only help here if you have a few ops of an interrupt handler to be saved from the (RT-wise) lousy caching architecture of ARM? [I threw coloured caches into the ring also to trigger some discussion on a long-term solution for MMU-based Xenomai on ARM.] Jan
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