From: Stefan Dirsch <[email protected]>
---
src/radeon_driver.c | 18 +++++++++++++++---
1 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 2cfe36a..18f7a57 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -222,6 +222,7 @@ struct RADEONInt10Save {
uint32_t MEM_CNTL;
uint32_t MEMSIZE;
uint32_t MPP_TB_CONFIG;
+ unsigned char MISC_OUT;
};
static Bool RADEONMapMMIO(ScrnInfoPtr pScrn);
@@ -277,14 +278,17 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t CardTmp;
- static struct RADEONInt10Save SaveStruct = { 0, 0, 0 };
+ static struct RADEONInt10Save SaveStruct = { 0, 0, 0, 0 };
if (!IS_AVIVO_VARIANT) {
+ OUTREG(0,RADEON_MEM_CNTL);
/* Save the values and zap MEM_CNTL */
SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
-
+#if !defined(__powerpc__) && !defined(__sparc__)
+ SaveStruct.MISC_OUT = inb(pScrn->domainIOBase + RADEON_GENMO_RD);
+#endif
/*
* Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4
*/
@@ -346,6 +350,14 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr)
CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u);
OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
}
+#if !defined(__powerpc__) && !defined(__sparc__)
+ if (CardTmp != pSave->MISC_OUT) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Restoring MiscOut (%x), setting to %x\n",
+ CardTmp, pSave->MEM_CNTL);
+ outb(pScrn->domainIOBase + RADEON_GENMO_WT, pSave->MISC_OUT);
+ }
+#endif
}
/* Allocate our private RADEONInfoRec */
@@ -3053,7 +3065,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
goto fail1;
}
-#if !defined(__alpha__)
+#if !defined(__alpha__) && !defined (__ia64__)
if (
#ifndef XSERVER_LIBPCIACCESS
xf86GetPciDomain(info->PciTag) ||
--
1.7.7
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