From: Stefan Dirsch <[email protected]>
See: https://bugzilla.novell.com/show_bug.cgi?id=155646
---
src/radeon_driver.c | 67 ++++++++++++++++++++++++++++++++++++++++++++------
1 files changed, 59 insertions(+), 8 deletions(-)
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 18f7a57..867e836 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -223,6 +223,7 @@ struct RADEONInt10Save {
uint32_t MEMSIZE;
uint32_t MPP_TB_CONFIG;
unsigned char MISC_OUT;
+ unsigned char ATTR[0x10];
};
static Bool RADEONMapMMIO(ScrnInfoPtr pScrn);
@@ -272,13 +273,67 @@ RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn)
return pPriv->ptr;
}
+#if !defined(__powerpc__) && !defined(__sparc__)
+/*
+ *
+ */
+void
+RADEONPreInt10SaveVGA(ScrnInfoPtr pScrn, struct RADEONInt10Save *pSave)
+{
+ IOADDRESS Base = pScrn->domainIOBase;
+ unsigned int Stat1Reg;
+ int i;
+
+ pSave->MISC_OUT = inb(pScrn->domainIOBase + RADEON_GENMO_RD);
+ Stat1Reg = (pSave->MISC_OUT & 0x1) ? 0x3DA : 0x3BA;
+ {
+ for (i = 0; i < 0x10; i++) {
+ inb(Base + Stat1Reg);
+ outb(Base + RADEON_ATTRX, i);
+ pSave->ATTR[i] = inb(Base + RADEON_ATTRDR);
+ }
+ }
+}
+
+/*
+ *
+ */
+void
+RADEONPostInt10CheckVGA(ScrnInfoPtr pScrn, struct RADEONInt10Save *pSave)
+{
+ IOADDRESS Base = pScrn->domainIOBase;
+ unsigned int Stat1Reg = (pSave->MISC_OUT & 0x1) ? 0x3DA : 0x3BA;
+ unsigned char CardTmp = inb(pScrn->domainIOBase + RADEON_GENMO_RD);
+ int i;
+
+ if (CardTmp != pSave->MISC_OUT) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Restoring MiscOut (%x), setting to %x\n",
+ CardTmp, pSave->MEM_CNTL);
+ outb(pScrn->domainIOBase + RADEON_GENMO_WT, pSave->MISC_OUT);
+ }
+
+ for (i = 0; i < 0x10; i++) {
+ inb(Base + Stat1Reg);
+ outb(Base + RADEON_ATTRX, i);
+ CardTmp = inb(Base + RADEON_ATTRDR);
+ if ( CardTmp != pSave->ATTR[i] ) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Restoring AttrReg[0x%i]: 0x%x to 0x%x\n",
+ i, CardTmp, pSave->ATTR[i]);
+ outb(Base + RADEON_ATTRDW, pSave->ATTR[i]);
+ }
+ }
+}
+#endif
+
static void
RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t CardTmp;
- static struct RADEONInt10Save SaveStruct = { 0, 0, 0, 0 };
+ static struct RADEONInt10Save SaveStruct = { 0, 0, 0, 0, {0} };
if (!IS_AVIVO_VARIANT) {
OUTREG(0,RADEON_MEM_CNTL);
@@ -286,8 +341,9 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr)
SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
+
#if !defined(__powerpc__) && !defined(__sparc__)
- SaveStruct.MISC_OUT = inb(pScrn->domainIOBase + RADEON_GENMO_RD);
+ RADEONPreInt10SaveVGA(pScrn, &SaveStruct);
#endif
/*
* Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4
@@ -351,12 +407,7 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr)
OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
}
#if !defined(__powerpc__) && !defined(__sparc__)
- if (CardTmp != pSave->MISC_OUT) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Restoring MiscOut (%x), setting to %x\n",
- CardTmp, pSave->MEM_CNTL);
- outb(pScrn->domainIOBase + RADEON_GENMO_WT, pSave->MISC_OUT);
- }
+ RADEONPostInt10CheckVGA(pScrn, pSave);
#endif
}
--
1.7.7
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