On Thu, 15 Aug 2002, Mark Vojkovich wrote:
> On Thu, 15 Aug 2002, Egbert Eich wrote:
>
> > Mark Vojkovich writes:
> > >
> > > To me the application of write_mem_barrier() to drivers like the
> > > "nv" driver seems almost haphazard. Can someone explain what the
> > > criteria is for placing these?
> > >
> >
> > These marcos are required only for weak ordering architectures
> > like Alpha and expand to nothing on architectures that don't
> > have this property. Ia32 is one of them.
> >
> > Generally you want to issue them to make sure all data has been
> > written to the bus before executing the next instruction.
> >
> > You want to do that before you read data from a register which
> > may depend on data written to another register previously.
>
> Can any two register writes get written out of order?
> If so, then the fences in the "nv" driver are misplaced and
> insufficient. For each primitive, the last register in the
> sequence is what initiates the drawing. If the setup writes
> were not commited before the kickoff write, things will be
> wrong.
>
>
> > Also you want to issue it before you write to a register that
> > starts an operation that depends on data written to other registers
> > and you want to issue this instruction afterwards to make sure the
> > operation actually gets initiated.
> >
> > That's the theory - generally it takes some experiments.
> >
> > We even don't know yet if all weak ordering architectures behave
> > exactly the same ie. if they require the fences at the same place.
> >
OK, after speaking with our PPC people here, I realize that
the nv driver is grossly misfenced. I will refence it.
Mark.
_______________________________________________
Xpert mailing list
[EMAIL PROTECTED]
http://XFree86.Org/mailman/listinfo/xpert
