Mark Vojkovich writes:
> On Thu, 15 Aug 2002, Egbert Eich wrote:
>
> Can any two register writes get written out of order?
They can, however this may depend on their address order.
If the address order is ascending you may be lucky.
I never went into this really deeply.
> If so, then the fences in the "nv" driver are misplaced and
> insufficient. For each primitive, the last register in the
> sequence is what initiates the drawing. If the setup writes
> were not commited before the kickoff write, things will be
> wrong.
Yes, that's the way it is done on a lot of chipsets.
Do you see any problems on a specific architecture?
I know that Jay Estabrook has done a lot of otpimization
for the Alpha - he may tell you more about the rules
where fence instructions need to be placed. But again
this may be architecture dependend.
>
>
>
> Well, here's the deal. Color expansion doesn't work reliably
> on PowerPC with the "nv" driver and there doesn't seem to be any reason
> for it other than architectural issues.
>
Have you tried adding some more fences? We may have to add
architecture specific fence macros :-((
I could try both Alpha and PPC as I can get access to both platforms
however I don't have time right now.
Regards,
Egbert.
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