Hi Jack,
Thanks to you and Danny Price for suggesting this. I copied over the
pcores in the zip file mentioned in the CASPER wiki to my
mlib_devel/xps_lib/XPS_ROACH_base/pcores directory, then I deleted the
previous r_spec_2048_r106 build directory, and then ran the compile again.
It fails with similar results. Here is the error message in the matlab
window:
Format revision of project to EDK 13.3 completed
ERROR:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: r_spec_2048_r106_even -
cannot
find MPD for the pcore 'opb_bram_if_cntlr_v1_00_a' in any of the
repositories
-
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 373
ERROR:EDK - IPNAME: opb_v20, INSTANCE: opb0 - cannot find MPD for the pcore
'opb_v20_v1_10_c' in any of the repositories -
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 99
ERROR:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: r_spec_2048_r106_even -
cannot
find MPD for the pcore 'opb_bram_if_cntlr_v1_00_a' in any of the
repositories
-
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 373
ERROR:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: r_spec_2048_r106_odd -
cannot
find MPD for the pcore 'opb_bram_if_cntlr_v1_00_a' in any of the
repositories
-
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 461
ERROR:EDK - IPNAME: opb_v20, INSTANCE: opb0 - cannot find MPD for the
pcore -
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 99
ERROR:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: r_spec_2048_r106_even -
cannot
find MPD for the pcore -
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 373
ERROR:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: r_spec_2048_r106_odd -
cannot
find MPD for the pcore -
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 461
ERROR:EDK - while loading XMP file
XPS% Evaluating file run_xps.tcl
ERROR:EDK - Load a MHS or XMP file first
Error using ==> gen_xps_files at 686
XPS failed.
I am attaching the r_spec_2048_r106/XPS_ROACH_base/system.mhs file with
this. Why is it not finding these pcores? There are some details
described in
http://www.xilinx.com/support/answers/34778.htm
But I am not sure which of those is applicable to my case.
Also, which directory should I copy the pcores from the
http://dl.dropbox.com/u/2832602/pcores_for_ise13.zip
zipfile:
1) mlib_devel/xps_lib/XPS_ROACH_base/pcores
or
2) mlib_devel/xps-lib/pcores
I did (1)
Thanks!
Gopal
On 05/10/2012 10:27 AM, Jack Hickish wrote:
Well, you wouldn't want things to be too easy now, would you? :)
Your missing pcore problem occurs because you are compiling with ISE
13.3, which removed support for some of the cores that we still use. The
design should compile fine with 11.x (which is what I tested it on), but
you can fix the error relatively easily -- see
https://casper.berkeley.edu/wiki/CASPER_With_ISE_13.1
Hopefully that will be the only hurdle,
Jack
On 10 May 2012 15:05, Gopal Narayanan <go...@astro.umass.edu
<mailto:go...@astro.umass.edu>> wrote:
Compilation of the MDL file for tutorial 3 in Jack's git repository
failed. The last few lines in the Matlab window after the failure are:
-------------
Format revision of project to EDK 13.3 completed
ERROR:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: r_spec_2048_r106_even
- cannot
find MPD for the pcore 'opb_bram_if_cntlr_v1_00_a' in any of the
repositories
-
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 373
WARNING:EDK - IPNAME: opb_v20, INSTANCE: opb0 - Superseded core for
architecture
'virtex5sx' -
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 99
ERROR:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: r_spec_2048_r106_even
- cannot
find MPD for the pcore 'opb_bram_if_cntlr_v1_00_a' in any of the
repositories
-
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 373
ERROR:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: r_spec_2048_r106_odd
- cannot
find MPD for the pcore 'opb_bram_if_cntlr_v1_00_a' in any of the
repositories
-
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 461
ERROR:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: r_spec_2048_r106_even
- cannot
find MPD for the pcore -
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 373
ERROR:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: r_spec_2048_r106_odd
- cannot
find MPD for the pcore -
/home/gopal/engineering/roach/myroach/r_spec_2048_r106/XPS_ROACH_base/system.
mhs line 461
ERROR:EDK - while loading XMP file
XPS% Evaluating file run_xps.tcl
ERROR:EDK - Load a MHS or XMP file first
Error using ==> gen_xps_files at 686
XPS failed.
-----------------
Looks like something in the BRAM block is causing the hiccups.
Thanks for looking into this.
Best Regards
Gopal
On 05/09/2012 03:58 PM, Jack Hickish wrote:
> Hi all,
>
> After a fair bit of tutorial related pain on the mailist
recently, I've
> just forked the tutorial-devel repo to
> https://github.com/jack-h/tutorials_devel and recompiled
tutorials 1-3
> with Sysgen 11.5 and the libraries in the main casper github repo.
>
> The tutorials in the 2011 directory *should* work (along with their
> python counterparts).
>
> Feel free to give those a go and give me a shout if you still
have problems.
>
> Cheers,
> Jack
>
> On 9 May 2012 20:49, John Ford <jf...@nrao.edu
<mailto:jf...@nrao.edu> <mailto:jf...@nrao.edu <mailto:jf...@nrao.edu>>>
> wrote:
>
> Hi all.
>
> Rich Lacasse at NRAO in Charlottesville has the same problem.
I also
> tried it on our machine in Green Bank, with the same bad
results.
> That's
> three separate machines and users with the same problem.
Something's
> wrong with this tutorial, or it is incompatible with the latest
> mlib_devel. Could someone have a look at it?
>
> Thanks!
>
> John
>
>
> > Hey Gopal,
> >
> > One thing you can try is to start matlab without loading the yellow
> > blocks,
> > open the model file and add them in fresh from the library,
save and
> > return
> > to normal usage.
> >
> > This will require you comment out the load xps_library portion
of your
> > matlab startup script. Start matlab, and open the desired
model file.
> > Doing this, you may be able to see the yellow blocks show up
as "bad
> > links" with red dashes around them. From there you can delete
> them, and
> > manually add them back in from the xps library. You may need to
> consult
> > the tutorial, or look at the original model .mdl file in a text
> editor, to
> > make sure you set the parameters appropriately. From there you
> should be
> > able to save the .mdl file, close matlab, go back to the startup
> file and
> > uncomment back to the regular usage. Hopefully it opens up
fine this
> > time.
> >
> >
> > If this solution works, perhaps I can write something more
> detailed to the
> > wiki page for the Tutorials. Would that be an appropriate edit
> for the
> > wiki? I think something stated on that page would help - we
have seen
> > several new roach users encounter this issue.
> >
> > Gopal, I was also strongly advised when I started out to use 11.5
> and the
> > stable release of the tools. This solution fixed the problem
on that
> > setup, hopefully it does on 13 as well.
> >
> > --Laura
> >
> > On Mon, May 7, 2012 at 12:44 PM, Gopal Narayanan
> > <go...@astro.umass.edu <mailto:go...@astro.umass.edu>
<mailto:go...@astro.umass.edu <mailto:go...@astro.umass.edu>>>wrote:
> >
> >> Hello All,
> >>
> >> I am running Matlab R2011A on a 64-bit Debian Linux System. I
> also have
> >> tested this issue in two other machines, one running Ubuntu (64
> bit as
> >> well), and the other running Windows XP-64 with similar
results. The
> >> Xilinx System Generator version in all cases is 13.3.4175.
> >>
> >> I have successfully created, compiled and programmed our ROACH
board
> >> with tutorials 1 and 2. I am able to download the tutorial model
> files
> >> from the CASPER website and open Tutorials 1 and 2, and
> compile/simulate
> >> them. However, when I download the r_spec_2048_103.mdl or the
> >> r_spec_2048_105.mdl (both are tutorial 3 files) from the
CASPER git
> >> site, and open within simulink, immediately I get a segfault
crash in
> >> matlab.
> >>
> >> I attach the crash dump for my ubuntu machine with this. I
contacted
> >> Matlab technical support, but after looking at it, they blame
Xilinx
> >> System Generator for this problem even indicating an url that
> apparently
> >> show memory leaks in sysgen:
> >>
> >> http://www.xilinx.com/support/answers/34287.htm
> >>
> >> I thought I would write to you all to find if anyone has had
> issues like
> >> mine. And if you have some helpful tips to fix the issue.
> Alternatively,
> >> if someone could send me an updated saved version of the tutorial
> 3 file
> >> saved with a more recent system generator version, I would
appreciate
> >> it! Maybe I could try with this updated version.
> >>
> >> Thanks a bunch.
> >>
> >> Gopal
> >> --
> >> Gopal Narayanan Ph #: (413) 545 0925
<tel:%28413%29%20545%200925>
> <tel:%28413%29%20545%200925>
> >> Department of Astronomy e-mail:
> go...@astro.umass.edu <mailto:go...@astro.umass.edu>
<mailto:go...@astro.umass.edu <mailto:go...@astro.umass.edu>>
> >> University of Massachusetts Amherst MA 01003
> >>
> >
>
>
>
>
--
Gopal Narayanan Ph #: (413) 545 0925
<tel:%28413%29%20545%200925>
Department of Astronomy e-mail:
go...@astro.umass.edu <mailto:go...@astro.umass.edu>
University of Massachusetts Amherst MA 01003
--
Gopal Narayanan Ph #: (413) 545 0925
Department of Astronomy e-mail: go...@astro.umass.edu
University of Massachusetts Amherst MA 01003
# ##############################################################################
# Target Board: ROACH v1.0
# Family: virtex5
# Device: xc5vlx110t
# Package: ff1136
# Speed Grade: -1
# Processor: None
# System clock frequency: 100.000000 MHz
# ##############################################################################
PARAMETER VERSION = 2.1.0
# Clock Ports
PORT sys_clk_n = sys_clk_n, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_clk_p = sys_clk_p, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT dly_clk_n = dly_clk_n, DIR = I, SIGIS = CLK, CLK_FREQ = 200000000
PORT dly_clk_p = dly_clk_p, DIR = I, SIGIS = CLK, CLK_FREQ = 200000000
PORT aux0_clk_n = aux0_clk_n, DIR = I, SIGIS = CLK, CLK_FREQ = 800000000
PORT aux0_clk_p = aux0_clk_p, DIR = I, SIGIS = CLK, CLK_FREQ = 800000000
PORT aux1_clk_n = aux1_clk_n, DIR = I, SIGIS = CLK, CLK_FREQ = 800000000
PORT aux1_clk_p = aux1_clk_p, DIR = I, SIGIS = CLK, CLK_FREQ = 800000000
# EPB Ports
PORT epb_clk_in = epb_clk_in, DIR = I
PORT epb_data = epb_data, DIR = IO, VEC = [15:0]
PORT epb_addr = epb_addr, DIR = I, VEC = [22:0]
PORT epb_addr_gp = epb_addr_gp, DIR = I, VEC = [5:0]
PORT epb_cs_n = epb_cs_n, DIR = I
PORT epb_be_n = epb_be_n, DIR = I, VEC = [1:0]
PORT epb_r_w_n = epb_r_w_n, DIR = I
PORT epb_oe_n = epb_oe_n, DIR = I
PORT epb_rdy = epb_rdy, DIR = O
PORT ppc_irq_n = ppc_irq_n, DIR = O
PORT adc0_adc3wire_clk = adc0_adc3wire_clk, DIR = O
PORT adc0_adc3wire_data = adc0_adc3wire_data, DIR = O
PORT adc0_adc3wire_strobe = adc0_adc3wire_strobe, DIR = O
PORT adc0_modepin = adc0_modepin, DIR = O
BEGIN roach_infrastructure
PARAMETER INSTANCE = infrastructure_inst
PARAMETER HW_VER = 1.00.a
PARAMETER CLK_FREQ = 800
PORT sys_clk_n = sys_clk_n
PORT sys_clk_p = sys_clk_p
PORT dly_clk_n = dly_clk_n
PORT dly_clk_p = dly_clk_p
PORT aux0_clk_n = aux0_clk_n
PORT aux0_clk_p = aux0_clk_p
PORT aux1_clk_n = aux1_clk_n
PORT aux1_clk_p = aux1_clk_p
PORT epb_clk_in = epb_clk_in
PORT sys_clk = sys_clk
PORT sys_clk90 = sys_clk90
PORT sys_clk180 = sys_clk180
PORT sys_clk270 = sys_clk270
PORT sys_clk_lock = sys_clk_lock
PORT sys_clk2x = sys_clk2x
PORT sys_clk2x90 = sys_clk2x90
PORT sys_clk2x180 = sys_clk2x180
PORT sys_clk2x270 = sys_clk2x270
PORT dly_clk = dly_clk
PORT aux0_clk = aux0_clk
PORT aux0_clk90 = aux0_clk90
PORT aux0_clk180 = aux0_clk180
PORT aux0_clk270 = aux0_clk270
PORT aux1_clk = aux1_clk
PORT aux1_clk90 = aux1_clk90
PORT aux1_clk180 = aux1_clk180
PORT aux1_clk270 = aux1_clk270
PORT aux0_clk2x = aux0_clk2x
PORT aux0_clk2x90 = aux0_clk2x90
PORT aux0_clk2x180 = aux0_clk2x180
PORT aux0_clk2x270 = aux0_clk2x270
PORT epb_clk = epb_clk
PORT idelay_rst = sys_reset
PORT idelay_rdy = idelay_rdy
END
BEGIN reset_block
PARAMETER INSTANCE = reset_block_inst
PARAMETER HW_VER = 1.00.a
PARAMETER DELAY = 10
PARAMETER WIDTH = 50
PORT clk = epb_clk
PORT async_reset_i = 0b0
PORT reset_i = 0b0
PORT reset_o = sys_reset
END
BEGIN opb_v20
PARAMETER INSTANCE = opb0
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_REG_GRANTS = 0
PORT SYS_Rst = 0b0
PORT OPB_Clk = epb_clk
END
BEGIN epb_opb_bridge
PARAMETER INSTANCE = epb_opb_bridge_inst
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE MOPB = opb0
PORT OPB_Clk = epb_clk
PORT sys_reset = 0b0
PORT epb_data_oe_n = epb_data_oe_n
PORT epb_cs_n = epb_cs_n_int
PORT epb_oe_n = epb_oe_n_int
PORT epb_r_w_n = epb_r_w_n_int
PORT epb_be_n = epb_be_n_int
PORT epb_addr = epb_addr_int
PORT epb_addr_gp = epb_addr_gp_int
PORT epb_data_i = epb_data_i
PORT epb_data_o = epb_data_o
PORT epb_rdy = epb_rdy_buf
PORT epb_rdy_oe = epb_rdy_oe
END
BEGIN epb_infrastructure
PARAMETER INSTANCE = epb_infrastructure_inst
PARAMETER HW_VER = 1.00.a
PORT epb_rdy_buf = epb_rdy
PORT epb_rdy = epb_rdy_buf
PORT epb_rdy_oe = epb_rdy_oe
PORT epb_data_buf = epb_data
PORT epb_data_oe_n_i = epb_data_oe_n
PORT epb_data_out_i = epb_data_o
PORT epb_data_in_o = epb_data_i
PORT epb_oe_n_buf = epb_oe_n
PORT epb_oe_n = epb_oe_n_int
PORT epb_cs_n_buf = epb_cs_n
PORT epb_cs_n = epb_cs_n_int
PORT epb_be_n_buf = epb_be_n
PORT epb_be_n = epb_be_n_int
PORT epb_r_w_n_buf = epb_r_w_n
PORT epb_r_w_n = epb_r_w_n_int
PORT epb_addr_buf = epb_addr
PORT epb_addr = epb_addr_int
PORT epb_addr_gp_buf = epb_addr_gp
PORT epb_addr_gp = epb_addr_gp_int
END
BEGIN sys_block
PARAMETER INSTANCE = sys_block_inst
PARAMETER HW_VER = 1.00.a
PARAMETER BOARD_ID = 0xB00B
PARAMETER REV_MAJOR = 0x1
PARAMETER REV_MINOR = 0x0
PARAMETER REV_RCS = 0x0
PARAMETER RCS_UPTODATE = 0x0
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000FFFF
BUS_INTERFACE SOPB = opb0
PORT OPB_Clk = epb_clk
PORT soft_reset = soft_reset
PORT irq_n = ppc_irq_n
PORT app_irq = 0x0000
PORT fab_clk = adc0_clk
END
BEGIN opb_adccontroller
PARAMETER INSTANCE = opb_adccontroller_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x00020000
PARAMETER C_HIGHADDR = 0x0002ffff
PARAMETER AUTOCONFIG_0 = 1
PARAMETER AUTOCONFIG_1 = 1
BUS_INTERFACE SOPB = opb0
PORT OPB_Clk = epb_clk
PORT adc0_adc3wire_clk = adc0_adc3wire_clk
PORT adc0_adc3wire_data = adc0_adc3wire_data
PORT adc0_adc3wire_strobe = adc0_adc3wire_strobe
PORT adc0_modepin = adc0_modepin
PORT adc0_ddrb = adc0_ddrb
PORT adc0_dcm_reset = adc0_dcm_reset
PORT adc0_psclk = adc0_psclk
PORT adc0_psen = adc0_psen
PORT adc0_psincdec = adc0_psincdec
PORT adc0_psdone = adc0_psdone
PORT adc0_clk = adc0_clk
END
##############################################
# User XSG IP core #
##############################################
BEGIN r_spec_2048_r106
PARAMETER INSTANCE = r_spec_2048_r106_XSG_core_config
PARAMETER HW_VER = 1.00.a
PORT clk = adc0_clk
PORT r_spec_2048_r106_acc_cnt_user_data_in =
r_spec_2048_r106_acc_cnt_user_data_in
PORT r_spec_2048_r106_acc_len_user_data_out =
r_spec_2048_r106_acc_len_user_data_out
PORT r_spec_2048_r106_adc_user_data_valid =
r_spec_2048_r106_adc_user_data_valid
PORT r_spec_2048_r106_adc_user_datai0 = r_spec_2048_r106_adc_user_datai0
PORT r_spec_2048_r106_adc_user_datai1 = r_spec_2048_r106_adc_user_datai1
PORT r_spec_2048_r106_adc_user_datai2 = r_spec_2048_r106_adc_user_datai2
PORT r_spec_2048_r106_adc_user_datai3 = r_spec_2048_r106_adc_user_datai3
PORT r_spec_2048_r106_adc_user_dataq0 = r_spec_2048_r106_adc_user_dataq0
PORT r_spec_2048_r106_adc_user_dataq1 = r_spec_2048_r106_adc_user_dataq1
PORT r_spec_2048_r106_adc_user_dataq2 = r_spec_2048_r106_adc_user_dataq2
PORT r_spec_2048_r106_adc_user_dataq3 = r_spec_2048_r106_adc_user_dataq3
PORT r_spec_2048_r106_adc_user_outofrangei0 =
r_spec_2048_r106_adc_user_outofrangei0
PORT r_spec_2048_r106_adc_user_outofrangei1 =
r_spec_2048_r106_adc_user_outofrangei1
PORT r_spec_2048_r106_adc_user_outofrangeq0 =
r_spec_2048_r106_adc_user_outofrangeq0
PORT r_spec_2048_r106_adc_user_outofrangeq1 =
r_spec_2048_r106_adc_user_outofrangeq1
PORT r_spec_2048_r106_adc_user_sync0 = r_spec_2048_r106_adc_user_sync0
PORT r_spec_2048_r106_adc_user_sync1 = r_spec_2048_r106_adc_user_sync1
PORT r_spec_2048_r106_adc_user_sync2 = r_spec_2048_r106_adc_user_sync2
PORT r_spec_2048_r106_adc_user_sync3 = r_spec_2048_r106_adc_user_sync3
PORT r_spec_2048_r106_cnt_rst_user_data_out =
r_spec_2048_r106_cnt_rst_user_data_out
PORT r_spec_2048_r106_even_data_out = r_spec_2048_r106_even_data_out
PORT r_spec_2048_r106_even_addr = r_spec_2048_r106_even_addr
PORT r_spec_2048_r106_even_data_in = r_spec_2048_r106_even_data_in
PORT r_spec_2048_r106_even_we = r_spec_2048_r106_even_we
PORT r_spec_2048_r106_gain_user_data_out = r_spec_2048_r106_gain_user_data_out
PORT r_spec_2048_r106_led0_sync_gateway = r_spec_2048_r106_led0_sync_gateway
PORT r_spec_2048_r106_led1_new_acc_gateway =
r_spec_2048_r106_led1_new_acc_gateway
PORT r_spec_2048_r106_led2_adc_clip_gateway =
r_spec_2048_r106_led2_adc_clip_gateway
PORT r_spec_2048_r106_odd_data_out = r_spec_2048_r106_odd_data_out
PORT r_spec_2048_r106_odd_addr = r_spec_2048_r106_odd_addr
PORT r_spec_2048_r106_odd_data_in = r_spec_2048_r106_odd_data_in
PORT r_spec_2048_r106_odd_we = r_spec_2048_r106_odd_we
PORT r_spec_2048_r106_sync_cnt_user_data_in =
r_spec_2048_r106_sync_cnt_user_data_in
END
############################
# Simulink interfaces #
############################
# r_spec_2048_r106/XSG core config
# r_spec_2048_r106/acc_cnt
BEGIN opb_register_simulink2ppc
PARAMETER INSTANCE = r_spec_2048_r106_acc_cnt
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x01000000
PARAMETER C_HIGHADDR = 0x010000FF
BUS_INTERFACE SOPB = opb0
PORT OPB_Clk = epb_clk
PORT user_data_in = r_spec_2048_r106_acc_cnt_user_data_in
PORT user_clk = adc0_clk
END
# r_spec_2048_r106/acc_len
BEGIN opb_register_ppc2simulink
PARAMETER INSTANCE = r_spec_2048_r106_acc_len
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x01000100
PARAMETER C_HIGHADDR = 0x010001FF
BUS_INTERFACE SOPB = opb0
PORT OPB_Clk = epb_clk
PORT user_data_out = r_spec_2048_r106_acc_len_user_data_out
PORT user_clk = adc0_clk
END
# r_spec_2048_r106/adc
BEGIN adc_interface
PARAMETER INSTANCE = r_spec_2048_r106_adc
PARAMETER HW_VER = 1.01.a
PORT user_data_valid = r_spec_2048_r106_adc_user_data_valid
PORT user_datai0 = r_spec_2048_r106_adc_user_datai0
PORT user_datai1 = r_spec_2048_r106_adc_user_datai1
PORT user_datai2 = r_spec_2048_r106_adc_user_datai2
PORT user_datai3 = r_spec_2048_r106_adc_user_datai3
PORT user_dataq0 = r_spec_2048_r106_adc_user_dataq0
PORT user_dataq1 = r_spec_2048_r106_adc_user_dataq1
PORT user_dataq2 = r_spec_2048_r106_adc_user_dataq2
PORT user_dataq3 = r_spec_2048_r106_adc_user_dataq3
PORT user_outofrangei0 = r_spec_2048_r106_adc_user_outofrangei0
PORT user_outofrangei1 = r_spec_2048_r106_adc_user_outofrangei1
PORT user_outofrangeq0 = r_spec_2048_r106_adc_user_outofrangeq0
PORT user_outofrangeq1 = r_spec_2048_r106_adc_user_outofrangeq1
PORT user_sync0 = r_spec_2048_r106_adc_user_sync0
PORT user_sync1 = r_spec_2048_r106_adc_user_sync1
PORT user_sync2 = r_spec_2048_r106_adc_user_sync2
PORT user_sync3 = r_spec_2048_r106_adc_user_sync3
PORT adc_clk_p = adc0clk_p
PORT adc_clk_n = adc0clk_n
PORT adc_sync_p = adc0sync_p
PORT adc_sync_n = adc0sync_n
PORT adc_outofrangei_p = adc0outofrangei_p
PORT adc_outofrangei_n = adc0outofrangei_n
PORT adc_outofrangeq_p = adc0outofrangeq_p
PORT adc_outofrangeq_n = adc0outofrangeq_n
PORT adc_dataeveni_p = adc0dataeveni_p
PORT adc_dataeveni_n = adc0dataeveni_n
PORT adc_dataoddi_p = adc0dataoddi_p
PORT adc_dataoddi_n = adc0dataoddi_n
PORT adc_dataevenq_p = adc0dataevenq_p
PORT adc_dataevenq_n = adc0dataevenq_n
PORT adc_dataoddq_p = adc0dataoddq_p
PORT adc_dataoddq_n = adc0dataoddq_n
PORT adc_ddrb_p = adc0ddrb_p
PORT adc_ddrb_n = adc0ddrb_n
PORT ctrl_reset = adc0_ddrb
PORT ctrl_clk_in = adc0_clk
PORT ctrl_clk_out = adc0_clk
PORT ctrl_clk90_out = adc0_clk90
PORT ctrl_dcm_locked = adc0_dcm_locked
PORT dcm_reset = adc0_dcm_reset
PORT dcm_psdone = adc0_psdone
PORT ctrl_clk180_out = adc0_clk180
PORT ctrl_clk270_out = adc0_clk270
PORT dcm_psclk = adc0_psclk
PORT dcm_psen = adc0_psen
PORT dcm_psincdec = adc0_psincdec
END
PORT adc0clk_p = adc0clk_p, DIR = in, SIGIS = CLK, CLK_FREQ = 800000000
PORT adc0clk_n = adc0clk_n, DIR = in, SIGIS = CLK, CLK_FREQ = 800000000
PORT adc0sync_p = adc0sync_p, DIR = in
PORT adc0sync_n = adc0sync_n, DIR = in
PORT adc0outofrangei_p = adc0outofrangei_p, DIR = in
PORT adc0outofrangei_n = adc0outofrangei_n, DIR = in
PORT adc0outofrangeq_p = adc0outofrangeq_p, DIR = in
PORT adc0outofrangeq_n = adc0outofrangeq_n, DIR = in
PORT adc0dataeveni_p = adc0dataeveni_p, DIR = in, VEC = [7:0]
PORT adc0dataeveni_n = adc0dataeveni_n, DIR = in, VEC = [7:0]
PORT adc0dataoddi_p = adc0dataoddi_p, DIR = in, VEC = [7:0]
PORT adc0dataoddi_n = adc0dataoddi_n, DIR = in, VEC = [7:0]
PORT adc0dataevenq_p = adc0dataevenq_p, DIR = in, VEC = [7:0]
PORT adc0dataevenq_n = adc0dataevenq_n, DIR = in, VEC = [7:0]
PORT adc0dataoddq_p = adc0dataoddq_p, DIR = in, VEC = [7:0]
PORT adc0dataoddq_n = adc0dataoddq_n, DIR = in, VEC = [7:0]
PORT adc0ddrb_p = adc0ddrb_p, DIR = out
PORT adc0ddrb_n = adc0ddrb_n, DIR = out
# r_spec_2048_r106/cnt_rst
BEGIN opb_register_ppc2simulink
PARAMETER INSTANCE = r_spec_2048_r106_cnt_rst
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x01000200
PARAMETER C_HIGHADDR = 0x010002FF
BUS_INTERFACE SOPB = opb0
PORT OPB_Clk = epb_clk
PORT user_data_out = r_spec_2048_r106_cnt_rst_user_data_out
PORT user_clk = adc0_clk
END
# r_spec_2048_r106/even
BEGIN bram_if
PARAMETER INSTANCE = r_spec_2048_r106_even_ramif
PARAMETER HW_VER = 1.00.a
PARAMETER ADDR_SIZE = 10
BUS_INTERFACE PORTA = r_spec_2048_r106_even_ramblk_porta
PORT clk_in = adc0_clk
PORT addr = r_spec_2048_r106_even_addr
PORT data_in = r_spec_2048_r106_even_data_in
PORT data_out = r_spec_2048_r106_even_data_out
PORT we = r_spec_2048_r106_even_we
END
BEGIN bram_block
PARAMETER INSTANCE = r_spec_2048_r106_even_ramblk
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = r_spec_2048_r106_even_ramblk_porta
BUS_INTERFACE PORTB = r_spec_2048_r106_even_ramblk_portb
END
BEGIN opb_bram_if_cntlr
PARAMETER INSTANCE = r_spec_2048_r106_even
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_BASEADDR = 0x01001000
PARAMETER C_HIGHADDR = 0x01001FFF
BUS_INTERFACE SOPB = opb0
BUS_INTERFACE PORTA = r_spec_2048_r106_even_ramblk_portb
END
# r_spec_2048_r106/gain
BEGIN opb_register_ppc2simulink
PARAMETER INSTANCE = r_spec_2048_r106_gain
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x01002000
PARAMETER C_HIGHADDR = 0x010020FF
BUS_INTERFACE SOPB = opb0
PORT OPB_Clk = epb_clk
PORT user_data_out = r_spec_2048_r106_gain_user_data_out
PORT user_clk = adc0_clk
END
# r_spec_2048_r106/led0_sync
BEGIN gpio_simulink2ext
PARAMETER INSTANCE = r_spec_2048_r106_led0_sync
PARAMETER HW_VER = 1.00.a
PARAMETER DDR = 0
PARAMETER WIDTH = 1
PARAMETER CLK_PHASE = 0
PARAMETER REG_IOB = true
PORT gateway = r_spec_2048_r106_led0_sync_gateway
PORT io_pad = r_spec_2048_r106_led0_sync_ext
PORT clk = adc0_clk
PORT clk90 = adc0_clk90
END
PORT r_spec_2048_r106_led0_sync_ext = r_spec_2048_r106_led0_sync_ext, DIR =
out, VEC = [0:0]
# r_spec_2048_r106/led1_new_acc
BEGIN gpio_simulink2ext
PARAMETER INSTANCE = r_spec_2048_r106_led1_new_acc
PARAMETER HW_VER = 1.00.a
PARAMETER DDR = 0
PARAMETER WIDTH = 1
PARAMETER CLK_PHASE = 0
PARAMETER REG_IOB = true
PORT gateway = r_spec_2048_r106_led1_new_acc_gateway
PORT io_pad = r_spec_2048_r106_led1_new_acc_ext
PORT clk = adc0_clk
PORT clk90 = adc0_clk90
END
PORT r_spec_2048_r106_led1_new_acc_ext = r_spec_2048_r106_led1_new_acc_ext, DIR
= out, VEC = [0:0]
# r_spec_2048_r106/led2_adc_clip
BEGIN gpio_simulink2ext
PARAMETER INSTANCE = r_spec_2048_r106_led2_adc_clip
PARAMETER HW_VER = 1.00.a
PARAMETER DDR = 0
PARAMETER WIDTH = 1
PARAMETER CLK_PHASE = 0
PARAMETER REG_IOB = true
PORT gateway = r_spec_2048_r106_led2_adc_clip_gateway
PORT io_pad = r_spec_2048_r106_led2_adc_clip_ext
PORT clk = adc0_clk
PORT clk90 = adc0_clk90
END
PORT r_spec_2048_r106_led2_adc_clip_ext = r_spec_2048_r106_led2_adc_clip_ext,
DIR = out, VEC = [0:0]
# r_spec_2048_r106/odd
BEGIN bram_if
PARAMETER INSTANCE = r_spec_2048_r106_odd_ramif
PARAMETER HW_VER = 1.00.a
PARAMETER ADDR_SIZE = 10
BUS_INTERFACE PORTA = r_spec_2048_r106_odd_ramblk_porta
PORT clk_in = adc0_clk
PORT addr = r_spec_2048_r106_odd_addr
PORT data_in = r_spec_2048_r106_odd_data_in
PORT data_out = r_spec_2048_r106_odd_data_out
PORT we = r_spec_2048_r106_odd_we
END
BEGIN bram_block
PARAMETER INSTANCE = r_spec_2048_r106_odd_ramblk
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = r_spec_2048_r106_odd_ramblk_porta
BUS_INTERFACE PORTB = r_spec_2048_r106_odd_ramblk_portb
END
BEGIN opb_bram_if_cntlr
PARAMETER INSTANCE = r_spec_2048_r106_odd
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_BASEADDR = 0x01003000
PARAMETER C_HIGHADDR = 0x01003FFF
BUS_INTERFACE SOPB = opb0
BUS_INTERFACE PORTA = r_spec_2048_r106_odd_ramblk_portb
END
# r_spec_2048_r106/sync_cnt
BEGIN opb_register_simulink2ppc
PARAMETER INSTANCE = r_spec_2048_r106_sync_cnt
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x01004000
PARAMETER C_HIGHADDR = 0x010040FF
BUS_INTERFACE SOPB = opb0
PORT OPB_Clk = epb_clk
PORT user_data_in = r_spec_2048_r106_sync_cnt_user_data_in
PORT user_clk = adc0_clk
END
