Hi all I have been working on a yellow block for the DDR3 of the ROACH-2. As far as I know this yellow block does not yet exist?
The same DRAM yellow block is used and interfacing the memory remains the same (as for the ROACH-1). The DRAM also uses an asynchronous fifo to allow long write bursts. I have tested the memory (thoroughly) using standard memory test patterns, and the memory passes reliably (I have yet to see a failure). I have not yet implemented a CPU interface to the DDR3, but this will hopefully be done soon. I have a couple more things that I would like to check/test, and if this is done I'll ask one of the SKA-SA guys to push this onto their CASPER mlib git repo. I thought this is information worth sharing so that multiple people don't end up working on the same thing... Hopefully this is not already the case! Thanks, JP van Rensburg
