Hi JP, We recently (last week) discovered we desperately need the DDR3 on ROACH2 since our work-around for getting the visibility data out of our system won't work in the long run (due to 10 GbE switch limiations... it's a long story). So just this week I re-started work on a DDR3 yellow block I had left behind a while ago.
I am using the ddr3_controller and ddr3_clk modules from github.com/ska-sa/roach2_test_gateware which I believe is known to work. Originally I used the wishbone bus that was used for testing the board with a bridge but the only OPB-to-WB bridge I found online had the memory addresses hard-coded into a netlist. Instead I took the opb_dram_sniffer (which contains arbitration between CPU and FPGA) and the async_dram pcores from ROACH-1 and am in the process of interfacing them to the above modules. I have not yet determined how to translate the old MIG application interface to the new one but came up with some hack that seems to compile. I haven't tested anything in hardware yet! I'm very happy that it seems I won't have to since JP's done all the work :) Also I'm completely fine with abandoning the very little work I've done to help JP on the CPU-interface side. If the current yellow block isn't online somewhere presently could I get a copy to use in testing the DDR3 on our ROACH2's? Thanks and good work! Rurik On Wed, Jul 24, 2013 at 7:02 AM, Jonathan Weintroub < jweintr...@cfa.harvard.edu> wrote: > Hi JP, Wes, > > We need the DDR3 rather urgently (time scale of 1 to 2 months), and Rurik > Primiani has recently been working on it. Laura Vertatschitsch will be > joining our group in September and we had her in mind to help with this too > though recently concluded her start date isn't soon enough. > > Of course these efforts should be coordinated, and your note, JP, is > certainly apropos and well timed for us. > > I'll leave it to Rurik to describe what he has been doing, he talked a bit > about bus interfaces, so perhaps the PPC comes into it. > > Cheers, > > Jonathan > > > On Jul 24, 2013, at 5:48 AM, Wesley New <wes...@ska.ac.za> wrote: > > > This is great work JP. > > > > Out of interest is anyone else planning to use the DDR3 on ROACH2? > > > > Wesley New > > South African SKA Project > > +2721 506 7365 > > www.ska.ac.za > > > > > > > > > > On Wed, Jul 24, 2013 at 8:24 AM, Juan-Pierre Jansen van Rensburg < > jvrensburg...@gmail.com> wrote: > > Hi all > > > > I have been working on a yellow block for the DDR3 of the ROACH-2. As > far as I know this yellow block does not yet exist? > > > > > > The same DRAM yellow block is used and interfacing the memory remains > the same (as for the ROACH-1). The DRAM also uses an asynchronous fifo to > allow long write bursts. I have tested the memory (thoroughly) using > standard memory test patterns, and the memory passes reliably (I have yet > to see a failure). > > > > I have not yet implemented a CPU interface to the DDR3, but this will > hopefully be done soon. I have a couple more things that I would like to > check/test, and if this is done I'll ask one of the SKA-SA guys to push > this onto their CASPER mlib git repo. > > > > I thought this is information worth sharing so that multiple people > don't end up working on the same thing... Hopefully this is not already the > case! > > > > Thanks, > > JP van Rensburg > > > > > > > > > > >
