Hi JP, Wes, We need the DDR3 rather urgently (time scale of 1 to 2 months), and Rurik Primiani has recently been working on it. Laura Vertatschitsch will be joining our group in September and we had her in mind to help with this too though recently concluded her start date isn't soon enough.
Of course these efforts should be coordinated, and your note, JP, is certainly apropos and well timed for us. I'll leave it to Rurik to describe what he has been doing, he talked a bit about bus interfaces, so perhaps the PPC comes into it. Cheers, Jonathan On Jul 24, 2013, at 5:48 AM, Wesley New <wes...@ska.ac.za> wrote: > This is great work JP. > > Out of interest is anyone else planning to use the DDR3 on ROACH2? > > Wesley New > South African SKA Project > +2721 506 7365 > www.ska.ac.za > > > > > On Wed, Jul 24, 2013 at 8:24 AM, Juan-Pierre Jansen van Rensburg > <jvrensburg...@gmail.com> wrote: > Hi all > > I have been working on a yellow block for the DDR3 of the ROACH-2. As far as > I know this yellow block does not yet exist? > > > The same DRAM yellow block is used and interfacing the memory remains the > same (as for the ROACH-1). The DRAM also uses an asynchronous fifo to allow > long write bursts. I have tested the memory (thoroughly) using standard > memory test patterns, and the memory passes reliably (I have yet to see a > failure). > > I have not yet implemented a CPU interface to the DDR3, but this will > hopefully be done soon. I have a couple more things that I would like to > check/test, and if this is done I'll ask one of the SKA-SA guys to push this > onto their CASPER mlib git repo. > > I thought this is information worth sharing so that multiple people don't end > up working on the same thing... Hopefully this is not already the case! > > Thanks, > JP van Rensburg > > > >
