Peter C. Wallace wrote: > > > The trick is that with double edged filtering and EPP 1.9, the FPGA controls > the timing so crosstalk causes no trouble for writes because the signals are > all quiet when the data is sampled. On reads the parallel port will sample > the > data near the edge of /WAIT. The /WAIT line has interleaved grounds in the > flat cable, avoiding wait/data crosstalk. > > > My main problem with lousy cables was that the computer end would see noise on the WAIT line and close out the IEEE-1284 cycle before the target board had even issued the rising edge of WAIT. I have since started putting terminations on all the communication signals on my boards, and that has cleaned up some of the crosstalk. I had to do this to get it to work with PCI parport cards, which use shorter delays. I will have to try some of these things out, and see if it looks different now (with the terminators).
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