This what I done in the bit file
-- the X stepgen is slaved to pins 4 and 5
constant PinDesc : PinDescType :=(
-- Base func sec unit sec func sec pin -- external DB25
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O
00 PIN 1 Spindle DAC PWM
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01
PIN 14 just GPIO
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O
02 PIN 2 X Step
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03
PIN 15 just GPIO
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O
04 PIN 3 X Dir
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O
05 PIN 16 Z Step
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O
06 PIN 4 S Step
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O
07 PIN 17 Z Dir
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O
08 PIN 5 S Dir
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O
09 PIN 6 Y Step
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O
10 PIN 7 Y Dir
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O
11 PIN 8 A Step
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O
12 PIN 9 A Dir
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13
PIN 10 Input 1 just GPIO
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O
14 PIN 11 Input 2 (Quad A)
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O
15 PIN 12 Input 3 (Quad B)
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O
16 PIN 13 Input 4 (Quad Idx)
On 2022/04/14 17:25, Peter C. Wallace wrote:
I suspect that you are right. For the sake of time running out I just
slaved the X stepgen in the bit file. I am using a simple trivkins
with no slave axis defined. The only issue now is that the DIR signal
on the slave has to be inverted somehow. Is there a way to NOT the
pin in the bit definition?
setp hm2_7i92.0.stepgen.xx.direction.invert_output true
Peter Wallace
Mesa Electronics
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Peter Wallace
Mesa Electronics
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