McKown, John wrote:
Since we are recalling the past, IIRC there was some CPU designed and
manufactured to natively execute p-code. It didn't really make a very
good showing in the market.
To be totally off topic: I really liked what I read about the Intel iAPX
432. Built from the ground up to be object oriented only.
http://www.sasktelwebsite.net/jbayko/cpu7.html
it was '79? or '81? asilomar acm sigops conference (i've lost my
proceedings over the years and don't have ready reference) .... the 432
guys gave a talk. i remember them mentioning was that a lot of
multiprocessor operation was hidden by the hardware ... you past process
units to the "hardware" ... and it kept track of how many processors
there were and which processes ran on which processors. it was
interesting since i had done something similar for m'code '75 for VAMPs
... a 5-way 370 smp project. ... misc. past postings mentioning VAMPs
project:
http://www.garlic.com/~lynn/subtopic.html#bounce
today it would be considered slightly analogous to what happens with LPARs.
The other thing they mentioned in the sigops talk was that all this high
-level function was dropped directly into 432 silicon ... and there was
no way of patching it ... short of shipping brand new silicon. That
characteristic was enuf to doom 432. i've got 3 old 432 intel books
http://www.garlic.com/~lynn/2000f.html#48 Famous Machines and Software
that didn't
the above post lists the following i432 books (in my basement) ... along
with quote from one of the intros mentioning b5000 from the 60s and also
referencing s/38
Introduction to the iAPX 432 Architecture (171821-001) copyright 1981, Intel
iAPX 432 Object Primer (171858-001, Rev. B)
iAPX 432 Interface Processor Architecture Reference Manual (171863-001)
....
there have been some number of other past discussions comparing 432 and
s/38 (aka as/400 precursor) ... as well as s/38 embodying several "FS"
features
http://www.garlic.com/~lynn/subtopic.html#futuresys
attached from long ago and far away (talking about vamps smp work from
1975). i had done dynamic adaptive resource management for cp67 as an
undergraduate in the 60s and then rereleased the "resource manager" for
vm370 on 11may76.
From: [EMAIL PROTECTED]
To: xxxxxxx
Date: 09/17/82--11:16:14
re: vamps;
I did all the design work & innovation for both the machine
architecture & operating system that made the number of real
processors relatively transparent
Dispatching & interruption was completely in the microcode (below the
machine interface). Essentially the number of processors were therefor
below the interface ... my feedback algorithms had to be beefed up to
allow for dynamically calculating the amount of CPU resources that
were currently available for consumption.
Turns out all the verbage in the Intel 432 document about number of
processors in a complex is transparent to the SCP. It can be
transparent from the standpoint of the dispatcher ... but the overall
resource allocation algorithms have to have a pretty good idea of the
amount of CPU resource available in the complex for doing a accurate
job.
... snip ...
misc. past posts mentioning 432
http://www.garlic.com/~lynn/2000d.html#57 iAPX-432 (was: 36 to 32 bit
transition
http://www.garlic.com/~lynn/2000d.html#62 iAPX-432 (was: 36 to 32 bit
transition
http://www.garlic.com/~lynn/2000e.html#6 Ridiculous
http://www.garlic.com/~lynn/2001g.html#36 What was object oriented in
iAPX432?
http://www.garlic.com/~lynn/2001k.html#2 Minimalist design (was Re:
Parity - why even or odd)
http://www.garlic.com/~lynn/2002d.html#27 iAPX432 today?
http://www.garlic.com/~lynn/2002d.html#46 IBM Mainframe at home
http://www.garlic.com/~lynn/2002l.html#19 Computer Architectures
http://www.garlic.com/~lynn/2002o.html#5 Anyone here ever use the iAPX432 ?
http://www.garlic.com/~lynn/2002q.html#11 computers and alcohol
http://www.garlic.com/~lynn/2003.html#5 vax6k.openecs.org rebirth
http://www.garlic.com/~lynn/2003.html#6 vax6k.openecs.org rebirth
http://www.garlic.com/~lynn/2003e.html#54 Reviving Multics
http://www.garlic.com/~lynn/2003e.html#55 Reviving Multics
http://www.garlic.com/~lynn/2003e.html#56 Reviving Multics
http://www.garlic.com/~lynn/2003m.html#23 Intel iAPX 432
http://www.garlic.com/~lynn/2003m.html#24 Intel iAPX 432
http://www.garlic.com/~lynn/2003m.html#47 Intel 860 and 960, was iAPX 432
http://www.garlic.com/~lynn/2003n.html#45 hung/zombie users ... long
boring, wandering story
http://www.garlic.com/~lynn/2004d.html#12 real multi-tasking, multi-
programming
http://www.garlic.com/~lynn/2004e.html#52 Infiniband - practicalities
for small clusters
http://www.garlic.com/~lynn/2004q.html#60 Will multicore CPUs have
identical cores?
http://www.garlic.com/~lynn/2004q.html#64 Will multicore CPUs have
identical cores?
http://www.garlic.com/~lynn/2004q.html#73 Athlon cache question
http://www.garlic.com/~lynn/2005d.html#64 Misuse of word "microcode"
http://www.garlic.com/~lynn/2005k.html#46 Performance and Capacity Planning
----------------------------------------------------------------------
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO
Search the archives at http://bama.ua.edu/archives/ibm-main.html
