On Thu, Oct 17, 2019 at 11:08 PM Christoph Hellwig <h...@lst.de> wrote: > > From: Damien Le Moal <damien.lem...@wdc.com> > > When in M-Mode, we can use the mhartid CSR to get the ID of the running > HART. Doing so, direct M-Mode boot without firmware is possible. > > Signed-off-by: Damien Le Moal <damien.lem...@wdc.com> > Signed-off-by: Christoph Hellwig <h...@lst.de> > Reviewed-by: Atish Patra <atish.pa...@wdc.com> > --- > arch/riscv/include/asm/csr.h | 1 + > arch/riscv/kernel/head.S | 8 ++++++++ > 2 files changed, 9 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 0dae5c361f29..d0b5113e1a54 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -81,6 +81,7 @@ > #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) > > /* symbolic CSR names: */ > +#define CSR_MHARTID 0xf14 > #define CSR_MSTATUS 0x300 > #define CSR_MIE 0x304 > #define CSR_MTVEC 0x305 > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S > index 679e63d29edb..583784cb3a32 100644 > --- a/arch/riscv/kernel/head.S > +++ b/arch/riscv/kernel/head.S > @@ -50,6 +50,14 @@ _start_kernel: > csrw CSR_XIE, zero > csrw CSR_XIP, zero > > +#ifdef CONFIG_RISCV_M_MODE > + /* > + * The hartid in a0 is expected later on, and we have no firmware > + * to hand it to us. > + */ > + csrr a0, CSR_MHARTID > +#endif > + > /* Load the global pointer */ > .option push > .option norelax > -- > 2.20.1 > > > _______________________________________________ > linux-riscv mailing list > linux-ri...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM. Reviewed-by: Anup Patel <a...@brainfault.org> Regards, Anup
