On Wed, Nov 14, 2007 at 10:44:20AM -0500, William Cohen wrote: > Andi Kleen wrote: > > >>One approach does not prevent the other. Assuming you allow cr4.pce, then > >>nothing prevents > >>a self-monitoring thread from reading the counters directly. You'll just > >>get the > >>lower 32-bit of it. So if you read frequently enough, you should not have > >>a problem. > > > >Hmm? RDPMC is 64bit. > > There are a number of processors that have 32-bit counters such as the IBM > power processors. On many x86 processors the upper bits of the counter are > sign extended from the lower 32 bits. Thus, one can only assume the lower > 32-bit are available. Roll over of values is quite possible (<2 seconds of > cycle count), so additional work needs to be done to obtain a valid value. >
Exactly, on Intel's only the bottom 32-bit actually are useable, the rest is sign-extension. That's why it is okay for measuring small sections of code, but that's it. On AMD, I think it is better. On Itanium you get the 47-bit worth. Don't know about Power or Cell. -- -Stephane - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
