Hi Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu <zhao1....@intel.com>
>
> The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
> for cpuid 0x8000001D") adds the cache topology for AMD CPU by encoding
> the number of sharing threads directly.
>
> From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14])
> means [1]:
>
> The number of logical processors sharing this cache is the value of
> this field incremented by 1. To determine which logical processors are
> sharing a cache, determine a Share Id for each processor as follows:
>
> ShareId = LocalApicId >> log2(NumSharingCache+1)
>
> Logical processors with the same ShareId then share a cache. If
> NumSharingCache+1 is not a power of two, round it up to the next power
> of two.
>
> From the description above, the caculation of this feild should be same
> as CPUID[4].EAX[bits 25:14] for intel cpus. So also use the offsets of
> APIC ID to calculate this field.
>
> Note: I don't have the AMD hardware available, hope folks can help me
> to test this, thanks!
Yes. Decode looks good. You can remove this note in next revision.
The subject line "Fix" gives wrong impression. I would change the subject
to (or something like this).
i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14]
>
> [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology
> Information
>
> Cc: Babu Moger <babu.mo...@amd.com>
> Signed-off-by: Zhao Liu <zhao1....@intel.com>
> ---
> Changes since v1:
> * Rename "l3_threads" to "num_apic_ids" in
> encode_cache_cpuid8000001d(). (Yanan)
> * Add the description of the original commit and add Cc.
> ---
> target/i386/cpu.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index c9897c0fe91a..f67b6be10b8d 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -361,7 +361,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo
> *cache,
> uint32_t *eax, uint32_t *ebx,
> uint32_t *ecx, uint32_t *edx)
> {
> - uint32_t l3_threads;
> + uint32_t num_apic_ids;
I would change it to match spec definition.
uint32_t num_sharing_cache;
> assert(cache->size == cache->line_size * cache->associativity *
> cache->partitions * cache->sets);
>
> @@ -370,13 +370,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo
> *cache,
>
> /* L3 is shared among multiple cores */
> if (cache->level == 3) {
> - l3_threads = topo_info->modules_per_die *
> - topo_info->cores_per_module *
> - topo_info->threads_per_core;
> - *eax |= (l3_threads - 1) << 14;
> + num_apic_ids = 1 << apicid_die_offset(topo_info);
> } else {
> - *eax |= ((topo_info->threads_per_core - 1) << 14);
> + num_apic_ids = 1 << apicid_core_offset(topo_info);
> }
> + *eax |= (num_apic_ids - 1) << 14;
>
> assert(cache->line_size > 0);
> assert(cache->partitions > 0);
--
Thanks
Babu Moger
