El 21/05/2011 17:15, Tobias Fröschle escribió:
- How is the communication designed (especially, how did you implement write access) to the ROM port?
It's a very old trick: I use 256 memory mapped ports: from $FE00 to $FEFF. When i want to write byte XX to the SPI interface, I make a read to the port $FEXX and discard the result.
- You seem to be planning to use a larger CPLD, could you add some select lines to implement more than one device on SPI?
It's in my plans to make the SPI interface available to be used for other purposes. Not now, because all my tests are being carried with the current interface hardware, whose CPLD has no free pins.
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