On 9/24/01 at 10:21 AM Malcolm Lear wrote:
>> It's not only the peripherals that are re-used - in fact,
>> everything but a part of the PCB slightly larger than the
>> size of the PGA package is reused.
>> The PCB was designed that way, it has distinct areas that
>> can be re-designed as needed. By now it must be obvious
>> why :-)
> Any chance of a subpanel for this area of the board to
> allow future flexibility.
I am not sure what you mean, Malcolm, but I guess you are talking about the
part with the CPU.
The GF PCB is composed of 5 areas. The PCB is the size of an Aurora, if you
look at the top layer, so that the J1 connector is along the right edge
(the same orientation it would be in when plugged into a regular QL), they
go like this:
1) Top right: power supply
2) Bottom right: Flash ROM and bus termination
3) Top mid: CPU area
4) Bottom mid: SDRAM and logic chip (this is also a sort of 'hub' where
everything connects)
5) Left: IO area.
This refers to the areas on the PCB - they cannot be separated mechanicaly,
a major upgrade would require a PCB redesign, but the 'sectored' approach
limits the amount of area that needs to be changed.
Between the CPU and the SDRAM/Logic area, there will be a connector, which
interfaces directly to the CPU bus, and alowes a second CPU or an upgrade
CPU, or even a peripheral that needs very high bandwidth, to be connected
to it - however, only ONE of these at the same time due to signal loading
and integrity. Although the 'vertical stacking' connection isn't very nice
mechanically - not a simple as a 'slot', but it ensures good signal
integrity because the signals are routed to very short lines.
I hope this answers some questions,
Nasta
