Re: [casper] ADC calibration issue

2017-03-30 Thread Jack Hickish 
Probably not, but the calibration is bitstream dependent. You've probably
found an edge case where the software fails, but it only occurs in one of
your designs.
In any case, it's good to know the hardware is ok.

Cheers
Jack

On Thu, 30 Mar 2017 at 13:43 vijay kumar 
wrote:

> Actually in my design, i am trying to capture adc values into a bram with
> adress with '16' and data width '8'
> . When I try to reduce the bram address widht to '8', this issue doesnt
> occur and adc calibration works fine. Is there anything wrong in the way I
> configure the brams ?
>
> On Thu, Mar 30, 2017 at 4:36 PM, vijay kumar  > wrote:
>
> The following is output I get when i type the 'git rev-parse HEAD':
>
> a949c9d5c1761078b4c884699ff52c1497a17ff6
>
> On Thu, Mar 30, 2017 at 2:32 PM, Mark Wagner  wrote:
>
> git rev-parse HEAD
>
> On Thu, Mar 30, 2017 at 10:46 AM, Jack Hickish 
> wrote:
>
> Someone better with git can tell you the "right" way, but I would just run
> "git log" in the repository directory, and note the most recent commit hash.
>
> Cheers
> Jack
>
> On Thu, 30 Mar 2017 at 10:31 vijay kumar 
> wrote:
>
> I am using 200 MHz ADC clock frequency (demux-1). And I am not sure how to
> check the adc repo and mlib_devel repo versions ? Could you please help me
> in that ?
> Thank you.
>
> On Wed, Mar 29, 2017 at 6:39 PM, Jack Hickish 
> wrote:
>
> I like the triumphant "done!" at the end :)
>
> Next questions --
> What version of the adc repo and mlib_devel repos are you using?
> Do you have other hardware you can test on? (It's very unlikely to be a
> hardware problem, IMO, but worth checking if you can).
> What ADC clock rate are you using?
>
> Cheers
> Jack
>
> On Wed, 29 Mar 2017 at 14:39 vijay kumar 
> wrote:
>
> Yes ! I assume the clock has been clocked. For convenience, I have
> included the output script i get after I run the initialization script.
>
>
> Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz...
> Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2)
> Gateware supports demux modes (using demux by 1)
> Resetting ADC, power cycling ADC, and reprogramming FPGA...
> ZDOK0 clock OK
> Calibrating SERDES blocks...calibrating chips ["A", "B", "C", "D"]
> chip A chan 1 lane 0 no good taps found
> chip A chan 1 lane 1 no good taps found
> chip A chan 2 lane 0 no good taps found
> chip A chan 2 lane 1 no good taps found
> chip A chan 3 lane 0 no good taps found
> chip A chan 3 lane 1 no good taps found
> chip A chan 4 lane 0 no good taps found
> chip A chan 4 lane 1 no good taps found
> chip B chan 1 lane 0 no good taps found
> chip B chan 1 lane 1 no good taps found
> chip B chan 2 lane 0 no good taps found
> chip B chan 2 lane 1 no good taps found
> chip B chan 3 lane 0 no good taps found
> chip B chan 3 lane 1 no good taps found
> chip B chan 4 lane 0 no good taps found
> chip B chan 4 lane 1 no good taps found
> chip C chan 1 lane 0 no good taps found
> chip C chan 1 lane 1 no good taps found
> chip C chan 2 lane 0 no good taps found
> chip C chan 2 lane 1 no good taps found
> chip C chan 3 lane 0 no good taps found
> chip C chan 3 lane 1 no good taps found
> chip C chan 4 lane 0 no good taps found
> chip C chan 4 lane 1 no good taps found
> chip D chan 1 lane 0 no good taps found
> chip D chan 1 lane 1 no good taps found
> chip D chan 2 lane 0 no good taps found
> chip D chan 2 lane 1 no good taps found
> chip D chan 3 lane 0 no good taps found
> chip D chan 3 lane 1 no good taps found
> chip D chan 4 lane 0 no good taps found
> chip D chan 4 lane 1 no good taps found
>
> ERROR: SERDES calibration failed for ADC A.
> ERROR: SERDES calibration failed for ADC B.
> ERROR: SERDES calibration failed for ADC C.
> ERROR: SERDES calibration failed for ADC D.
> Selecting analog inputs...
> Using default digital gain of 1...
> Done!
>
>
> On Wed, Mar 29, 2017 at 5:33 PM, Jack Hickish 
> wrote:
>
> Further, is the board clocking OK? -- I believe the initialization script
> should give feedback on whether of not the FPGA's PLL has successfully
> locked to the ADC clock, and what the current measured board clock is.
>
> Cheers
> Jack
>
> On Wed, 29 Mar 2017 at 14:28 Matt Dexter  wrote:
>
> Is the design and lab setup consistent with the limitations documented at
>
> https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Rate_vs_Virtex-6_MMCM_Limitations
> ?
>
> More information on the clock requirements may be found at
>
> https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#ADC16x250-8_coax_rev_2_Inputs
>
> Matt
>
> On Wed, 29 Mar 2017, vijay kumar wrote:
>
> > Date: Wed, 29 Mar 2017 17:16:34 -0400
> > From: vijay kumar 
> > To: casper@lists.berkeley.edu
> > Subject: [casper] ADC calibration issue
> >
> > Hello Casperites,
> > I have been

Re: [casper] ADC calibration issue

2017-03-30 Thread vijay kumar 
Actually in my design, i am trying to capture adc values into a bram with
adress with '16' and data width '8'
. When I try to reduce the bram address widht to '8', this issue doesnt
occur and adc calibration works fine. Is there anything wrong in the way I
configure the brams ?

On Thu, Mar 30, 2017 at 4:36 PM, vijay kumar 
wrote:

> The following is output I get when i type the 'git rev-parse HEAD':
>
> a949c9d5c1761078b4c884699ff52c1497a17ff6
>
> On Thu, Mar 30, 2017 at 2:32 PM, Mark Wagner  wrote:
>
>> git rev-parse HEAD
>>
>> On Thu, Mar 30, 2017 at 10:46 AM, Jack Hickish 
>> wrote:
>>
>>> Someone better with git can tell you the "right" way, but I would just
>>> run "git log" in the repository directory, and note the most recent commit
>>> hash.
>>>
>>> Cheers
>>> Jack
>>>
>>> On Thu, 30 Mar 2017 at 10:31 vijay kumar 
>>> wrote:
>>>
 I am using 200 MHz ADC clock frequency (demux-1). And I am not sure how
 to check the adc repo and mlib_devel repo versions ? Could you please help
 me in that ?
 Thank you.

 On Wed, Mar 29, 2017 at 6:39 PM, Jack Hickish 
 wrote:

 I like the triumphant "done!" at the end :)

 Next questions --
 What version of the adc repo and mlib_devel repos are you using?
 Do you have other hardware you can test on? (It's very unlikely to be a
 hardware problem, IMO, but worth checking if you can).
 What ADC clock rate are you using?

 Cheers
 Jack

 On Wed, 29 Mar 2017 at 14:39 vijay kumar 
 wrote:

 Yes ! I assume the clock has been clocked. For convenience, I have
 included the output script i get after I run the initialization script.


 Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz...
 Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2)
 Gateware supports demux modes (using demux by 1)
 Resetting ADC, power cycling ADC, and reprogramming FPGA...
 ZDOK0 clock OK
 Calibrating SERDES blocks...calibrating chips ["A", "B", "C", "D"]
 chip A chan 1 lane 0 no good taps found
 chip A chan 1 lane 1 no good taps found
 chip A chan 2 lane 0 no good taps found
 chip A chan 2 lane 1 no good taps found
 chip A chan 3 lane 0 no good taps found
 chip A chan 3 lane 1 no good taps found
 chip A chan 4 lane 0 no good taps found
 chip A chan 4 lane 1 no good taps found
 chip B chan 1 lane 0 no good taps found
 chip B chan 1 lane 1 no good taps found
 chip B chan 2 lane 0 no good taps found
 chip B chan 2 lane 1 no good taps found
 chip B chan 3 lane 0 no good taps found
 chip B chan 3 lane 1 no good taps found
 chip B chan 4 lane 0 no good taps found
 chip B chan 4 lane 1 no good taps found
 chip C chan 1 lane 0 no good taps found
 chip C chan 1 lane 1 no good taps found
 chip C chan 2 lane 0 no good taps found
 chip C chan 2 lane 1 no good taps found
 chip C chan 3 lane 0 no good taps found
 chip C chan 3 lane 1 no good taps found
 chip C chan 4 lane 0 no good taps found
 chip C chan 4 lane 1 no good taps found
 chip D chan 1 lane 0 no good taps found
 chip D chan 1 lane 1 no good taps found
 chip D chan 2 lane 0 no good taps found
 chip D chan 2 lane 1 no good taps found
 chip D chan 3 lane 0 no good taps found
 chip D chan 3 lane 1 no good taps found
 chip D chan 4 lane 0 no good taps found
 chip D chan 4 lane 1 no good taps found

 ERROR: SERDES calibration failed for ADC A.
 ERROR: SERDES calibration failed for ADC B.
 ERROR: SERDES calibration failed for ADC C.
 ERROR: SERDES calibration failed for ADC D.
 Selecting analog inputs...
 Using default digital gain of 1...
 Done!


 On Wed, Mar 29, 2017 at 5:33 PM, Jack Hickish 
 wrote:

 Further, is the board clocking OK? -- I believe the initialization
 script should give feedback on whether of not the FPGA's PLL has
 successfully locked to the ADC clock, and what the current measured board
 clock is.

 Cheers
 Jack

 On Wed, 29 Mar 2017 at 14:28 Matt Dexter  wrote:

 Is the design and lab setup consistent with the limitations documented
 at
 https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Ra
 te_vs_Virtex-6_MMCM_Limitations
 ?

 More information on the clock requirements may be found at
 https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#ADC1
 6x250-8_coax_rev_2_Inputs

 Matt

 On Wed, 29 Mar 2017, vijay kumar wrote:

 > Date: Wed, 29 Mar 2017 17:16:34 -0400
 > From: vijay kumar 
 > To: casper@lists.berkeley.edu
 > Subject: [casper] ADC calibration issue
 >
 >

Re: [casper] ADC calibration issue

2017-03-30 Thread vijay kumar 
The following is output I get when i type the 'git rev-parse HEAD':

a949c9d5c1761078b4c884699ff52c1497a17ff6

On Thu, Mar 30, 2017 at 2:32 PM, Mark Wagner  wrote:

> git rev-parse HEAD
>
> On Thu, Mar 30, 2017 at 10:46 AM, Jack Hickish 
> wrote:
>
>> Someone better with git can tell you the "right" way, but I would just
>> run "git log" in the repository directory, and note the most recent commit
>> hash.
>>
>> Cheers
>> Jack
>>
>> On Thu, 30 Mar 2017 at 10:31 vijay kumar 
>> wrote:
>>
>>> I am using 200 MHz ADC clock frequency (demux-1). And I am not sure how
>>> to check the adc repo and mlib_devel repo versions ? Could you please help
>>> me in that ?
>>> Thank you.
>>>
>>> On Wed, Mar 29, 2017 at 6:39 PM, Jack Hickish 
>>> wrote:
>>>
>>> I like the triumphant "done!" at the end :)
>>>
>>> Next questions --
>>> What version of the adc repo and mlib_devel repos are you using?
>>> Do you have other hardware you can test on? (It's very unlikely to be a
>>> hardware problem, IMO, but worth checking if you can).
>>> What ADC clock rate are you using?
>>>
>>> Cheers
>>> Jack
>>>
>>> On Wed, 29 Mar 2017 at 14:39 vijay kumar 
>>> wrote:
>>>
>>> Yes ! I assume the clock has been clocked. For convenience, I have
>>> included the output script i get after I run the initialization script.
>>>
>>>
>>> Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz...
>>> Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2)
>>> Gateware supports demux modes (using demux by 1)
>>> Resetting ADC, power cycling ADC, and reprogramming FPGA...
>>> ZDOK0 clock OK
>>> Calibrating SERDES blocks...calibrating chips ["A", "B", "C", "D"]
>>> chip A chan 1 lane 0 no good taps found
>>> chip A chan 1 lane 1 no good taps found
>>> chip A chan 2 lane 0 no good taps found
>>> chip A chan 2 lane 1 no good taps found
>>> chip A chan 3 lane 0 no good taps found
>>> chip A chan 3 lane 1 no good taps found
>>> chip A chan 4 lane 0 no good taps found
>>> chip A chan 4 lane 1 no good taps found
>>> chip B chan 1 lane 0 no good taps found
>>> chip B chan 1 lane 1 no good taps found
>>> chip B chan 2 lane 0 no good taps found
>>> chip B chan 2 lane 1 no good taps found
>>> chip B chan 3 lane 0 no good taps found
>>> chip B chan 3 lane 1 no good taps found
>>> chip B chan 4 lane 0 no good taps found
>>> chip B chan 4 lane 1 no good taps found
>>> chip C chan 1 lane 0 no good taps found
>>> chip C chan 1 lane 1 no good taps found
>>> chip C chan 2 lane 0 no good taps found
>>> chip C chan 2 lane 1 no good taps found
>>> chip C chan 3 lane 0 no good taps found
>>> chip C chan 3 lane 1 no good taps found
>>> chip C chan 4 lane 0 no good taps found
>>> chip C chan 4 lane 1 no good taps found
>>> chip D chan 1 lane 0 no good taps found
>>> chip D chan 1 lane 1 no good taps found
>>> chip D chan 2 lane 0 no good taps found
>>> chip D chan 2 lane 1 no good taps found
>>> chip D chan 3 lane 0 no good taps found
>>> chip D chan 3 lane 1 no good taps found
>>> chip D chan 4 lane 0 no good taps found
>>> chip D chan 4 lane 1 no good taps found
>>>
>>> ERROR: SERDES calibration failed for ADC A.
>>> ERROR: SERDES calibration failed for ADC B.
>>> ERROR: SERDES calibration failed for ADC C.
>>> ERROR: SERDES calibration failed for ADC D.
>>> Selecting analog inputs...
>>> Using default digital gain of 1...
>>> Done!
>>>
>>>
>>> On Wed, Mar 29, 2017 at 5:33 PM, Jack Hickish 
>>> wrote:
>>>
>>> Further, is the board clocking OK? -- I believe the initialization
>>> script should give feedback on whether of not the FPGA's PLL has
>>> successfully locked to the ADC clock, and what the current measured board
>>> clock is.
>>>
>>> Cheers
>>> Jack
>>>
>>> On Wed, 29 Mar 2017 at 14:28 Matt Dexter  wrote:
>>>
>>> Is the design and lab setup consistent with the limitations documented at
>>> https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Ra
>>> te_vs_Virtex-6_MMCM_Limitations
>>> ?
>>>
>>> More information on the clock requirements may be found at
>>> https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#ADC1
>>> 6x250-8_coax_rev_2_Inputs
>>>
>>> Matt
>>>
>>> On Wed, 29 Mar 2017, vijay kumar wrote:
>>>
>>> > Date: Wed, 29 Mar 2017 17:16:34 -0400
>>> > From: vijay kumar 
>>> > To: casper@lists.berkeley.edu
>>> > Subject: [casper] ADC calibration issue
>>> >
>>> > Hello Casperites,
>>> > I have been working on the ROACH-2 casper for the past few months. Now
>>> i have started to capture values from the ADC
>>> > 16x250-8 block. But, when I am trying to run the initialization
>>> script, it gives me an error saying that "chip 'x'
>>> > chan 'x' lane 'x' no good taps found  ". I am unable to figure out
>>> what might be causing this error. I would be glad
>>> > if I could get help from you guys.
>>> >
>>> > Thank you.
>>> >
>>> >
>>> > With regards
>>> >

Re: [casper] ADC calibration issue

2017-03-30 Thread Mark Wagner 
git rev-parse HEAD

On Thu, Mar 30, 2017 at 10:46 AM, Jack Hickish 
wrote:

> Someone better with git can tell you the "right" way, but I would just run
> "git log" in the repository directory, and note the most recent commit hash.
>
> Cheers
> Jack
>
> On Thu, 30 Mar 2017 at 10:31 vijay kumar 
> wrote:
>
>> I am using 200 MHz ADC clock frequency (demux-1). And I am not sure how
>> to check the adc repo and mlib_devel repo versions ? Could you please help
>> me in that ?
>> Thank you.
>>
>> On Wed, Mar 29, 2017 at 6:39 PM, Jack Hickish 
>> wrote:
>>
>> I like the triumphant "done!" at the end :)
>>
>> Next questions --
>> What version of the adc repo and mlib_devel repos are you using?
>> Do you have other hardware you can test on? (It's very unlikely to be a
>> hardware problem, IMO, but worth checking if you can).
>> What ADC clock rate are you using?
>>
>> Cheers
>> Jack
>>
>> On Wed, 29 Mar 2017 at 14:39 vijay kumar 
>> wrote:
>>
>> Yes ! I assume the clock has been clocked. For convenience, I have
>> included the output script i get after I run the initialization script.
>>
>>
>> Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz...
>> Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2)
>> Gateware supports demux modes (using demux by 1)
>> Resetting ADC, power cycling ADC, and reprogramming FPGA...
>> ZDOK0 clock OK
>> Calibrating SERDES blocks...calibrating chips ["A", "B", "C", "D"]
>> chip A chan 1 lane 0 no good taps found
>> chip A chan 1 lane 1 no good taps found
>> chip A chan 2 lane 0 no good taps found
>> chip A chan 2 lane 1 no good taps found
>> chip A chan 3 lane 0 no good taps found
>> chip A chan 3 lane 1 no good taps found
>> chip A chan 4 lane 0 no good taps found
>> chip A chan 4 lane 1 no good taps found
>> chip B chan 1 lane 0 no good taps found
>> chip B chan 1 lane 1 no good taps found
>> chip B chan 2 lane 0 no good taps found
>> chip B chan 2 lane 1 no good taps found
>> chip B chan 3 lane 0 no good taps found
>> chip B chan 3 lane 1 no good taps found
>> chip B chan 4 lane 0 no good taps found
>> chip B chan 4 lane 1 no good taps found
>> chip C chan 1 lane 0 no good taps found
>> chip C chan 1 lane 1 no good taps found
>> chip C chan 2 lane 0 no good taps found
>> chip C chan 2 lane 1 no good taps found
>> chip C chan 3 lane 0 no good taps found
>> chip C chan 3 lane 1 no good taps found
>> chip C chan 4 lane 0 no good taps found
>> chip C chan 4 lane 1 no good taps found
>> chip D chan 1 lane 0 no good taps found
>> chip D chan 1 lane 1 no good taps found
>> chip D chan 2 lane 0 no good taps found
>> chip D chan 2 lane 1 no good taps found
>> chip D chan 3 lane 0 no good taps found
>> chip D chan 3 lane 1 no good taps found
>> chip D chan 4 lane 0 no good taps found
>> chip D chan 4 lane 1 no good taps found
>>
>> ERROR: SERDES calibration failed for ADC A.
>> ERROR: SERDES calibration failed for ADC B.
>> ERROR: SERDES calibration failed for ADC C.
>> ERROR: SERDES calibration failed for ADC D.
>> Selecting analog inputs...
>> Using default digital gain of 1...
>> Done!
>>
>>
>> On Wed, Mar 29, 2017 at 5:33 PM, Jack Hickish 
>> wrote:
>>
>> Further, is the board clocking OK? -- I believe the initialization script
>> should give feedback on whether of not the FPGA's PLL has successfully
>> locked to the ADC clock, and what the current measured board clock is.
>>
>> Cheers
>> Jack
>>
>> On Wed, 29 Mar 2017 at 14:28 Matt Dexter  wrote:
>>
>> Is the design and lab setup consistent with the limitations documented at
>> https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_
>> Rate_vs_Virtex-6_MMCM_Limitations
>> ?
>>
>> More information on the clock requirements may be found at
>> https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#
>> ADC16x250-8_coax_rev_2_Inputs
>>
>> Matt
>>
>> On Wed, 29 Mar 2017, vijay kumar wrote:
>>
>> > Date: Wed, 29 Mar 2017 17:16:34 -0400
>> > From: vijay kumar 
>> > To: casper@lists.berkeley.edu
>> > Subject: [casper] ADC calibration issue
>> >
>> > Hello Casperites,
>> > I have been working on the ROACH-2 casper for the past few months. Now
>> i have started to capture values from the ADC
>> > 16x250-8 block. But, when I am trying to run the initialization script,
>> it gives me an error saying that "chip 'x'
>> > chan 'x' lane 'x' no good taps found  ". I am unable to figure out what
>> might be causing this error. I would be glad
>> > if I could get help from you guys.
>> >
>> > Thank you.
>> >
>> >
>> > With regards
>> > Vijay
>> >
>> > --
>> > You received this message because you are subscribed to the Google
>> Groups "casper@lists.berkeley.edu" group.
>> > To unsubscribe from this group and stop receiving emails from it, send
>> an email to
>> > casper+unsubscr...@lists.berkeley.edu.
>> > To post to this group, send email to

Re: [casper] ADC calibration issue

2017-03-30 Thread Jack Hickish 
Someone better with git can tell you the "right" way, but I would just run
"git log" in the repository directory, and note the most recent commit hash.

Cheers
Jack

On Thu, 30 Mar 2017 at 10:31 vijay kumar 
wrote:

> I am using 200 MHz ADC clock frequency (demux-1). And I am not sure how to
> check the adc repo and mlib_devel repo versions ? Could you please help me
> in that ?
> Thank you.
>
> On Wed, Mar 29, 2017 at 6:39 PM, Jack Hickish 
> wrote:
>
> I like the triumphant "done!" at the end :)
>
> Next questions --
> What version of the adc repo and mlib_devel repos are you using?
> Do you have other hardware you can test on? (It's very unlikely to be a
> hardware problem, IMO, but worth checking if you can).
> What ADC clock rate are you using?
>
> Cheers
> Jack
>
> On Wed, 29 Mar 2017 at 14:39 vijay kumar 
> wrote:
>
> Yes ! I assume the clock has been clocked. For convenience, I have
> included the output script i get after I run the initialization script.
>
>
> Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz...
> Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2)
> Gateware supports demux modes (using demux by 1)
> Resetting ADC, power cycling ADC, and reprogramming FPGA...
> ZDOK0 clock OK
> Calibrating SERDES blocks...calibrating chips ["A", "B", "C", "D"]
> chip A chan 1 lane 0 no good taps found
> chip A chan 1 lane 1 no good taps found
> chip A chan 2 lane 0 no good taps found
> chip A chan 2 lane 1 no good taps found
> chip A chan 3 lane 0 no good taps found
> chip A chan 3 lane 1 no good taps found
> chip A chan 4 lane 0 no good taps found
> chip A chan 4 lane 1 no good taps found
> chip B chan 1 lane 0 no good taps found
> chip B chan 1 lane 1 no good taps found
> chip B chan 2 lane 0 no good taps found
> chip B chan 2 lane 1 no good taps found
> chip B chan 3 lane 0 no good taps found
> chip B chan 3 lane 1 no good taps found
> chip B chan 4 lane 0 no good taps found
> chip B chan 4 lane 1 no good taps found
> chip C chan 1 lane 0 no good taps found
> chip C chan 1 lane 1 no good taps found
> chip C chan 2 lane 0 no good taps found
> chip C chan 2 lane 1 no good taps found
> chip C chan 3 lane 0 no good taps found
> chip C chan 3 lane 1 no good taps found
> chip C chan 4 lane 0 no good taps found
> chip C chan 4 lane 1 no good taps found
> chip D chan 1 lane 0 no good taps found
> chip D chan 1 lane 1 no good taps found
> chip D chan 2 lane 0 no good taps found
> chip D chan 2 lane 1 no good taps found
> chip D chan 3 lane 0 no good taps found
> chip D chan 3 lane 1 no good taps found
> chip D chan 4 lane 0 no good taps found
> chip D chan 4 lane 1 no good taps found
>
> ERROR: SERDES calibration failed for ADC A.
> ERROR: SERDES calibration failed for ADC B.
> ERROR: SERDES calibration failed for ADC C.
> ERROR: SERDES calibration failed for ADC D.
> Selecting analog inputs...
> Using default digital gain of 1...
> Done!
>
>
> On Wed, Mar 29, 2017 at 5:33 PM, Jack Hickish 
> wrote:
>
> Further, is the board clocking OK? -- I believe the initialization script
> should give feedback on whether of not the FPGA's PLL has successfully
> locked to the ADC clock, and what the current measured board clock is.
>
> Cheers
> Jack
>
> On Wed, 29 Mar 2017 at 14:28 Matt Dexter  wrote:
>
> Is the design and lab setup consistent with the limitations documented at
>
> https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Rate_vs_Virtex-6_MMCM_Limitations
> ?
>
> More information on the clock requirements may be found at
>
> https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#ADC16x250-8_coax_rev_2_Inputs
>
> Matt
>
> On Wed, 29 Mar 2017, vijay kumar wrote:
>
> > Date: Wed, 29 Mar 2017 17:16:34 -0400
> > From: vijay kumar 
> > To: casper@lists.berkeley.edu
> > Subject: [casper] ADC calibration issue
> >
> > Hello Casperites,
> > I have been working on the ROACH-2 casper for the past few months. Now i
> have started to capture values from the ADC
> > 16x250-8 block. But, when I am trying to run the initialization script,
> it gives me an error saying that "chip 'x'
> > chan 'x' lane 'x' no good taps found  ". I am unable to figure out what
> might be causing this error. I would be glad
> > if I could get help from you guys.
> >
> > Thank you.
> >
> >
> > With regards
> > Vijay
> >
> > --
> > You received this message because you are subscribed to the Google
> Groups "casper@lists.berkeley.edu" group.
> > To unsubscribe from this group and stop receiving emails from it, send
> an email to
> > casper+unsubscr...@lists.berkeley.edu.
> > To post to this group, send email to casper@lists.berkeley.edu.
> >
> >
>
> --
> You received this message because you are subscribed to the Google Groups "
> casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to

Re: [casper] ADC calibration issue

2017-03-30 Thread vijay kumar 
I am using 200 MHz ADC clock frequency (demux-1). And I am not sure how to
check the adc repo and mlib_devel repo versions ? Could you please help me
in that ?
Thank you.

On Wed, Mar 29, 2017 at 6:39 PM, Jack Hickish  wrote:

> I like the triumphant "done!" at the end :)
>
> Next questions --
> What version of the adc repo and mlib_devel repos are you using?
> Do you have other hardware you can test on? (It's very unlikely to be a
> hardware problem, IMO, but worth checking if you can).
> What ADC clock rate are you using?
>
> Cheers
> Jack
>
> On Wed, 29 Mar 2017 at 14:39 vijay kumar 
> wrote:
>
>> Yes ! I assume the clock has been clocked. For convenience, I have
>> included the output script i get after I run the initialization script.
>>
>>
>> Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz...
>> Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2)
>> Gateware supports demux modes (using demux by 1)
>> Resetting ADC, power cycling ADC, and reprogramming FPGA...
>> ZDOK0 clock OK
>> Calibrating SERDES blocks...calibrating chips ["A", "B", "C", "D"]
>> chip A chan 1 lane 0 no good taps found
>> chip A chan 1 lane 1 no good taps found
>> chip A chan 2 lane 0 no good taps found
>> chip A chan 2 lane 1 no good taps found
>> chip A chan 3 lane 0 no good taps found
>> chip A chan 3 lane 1 no good taps found
>> chip A chan 4 lane 0 no good taps found
>> chip A chan 4 lane 1 no good taps found
>> chip B chan 1 lane 0 no good taps found
>> chip B chan 1 lane 1 no good taps found
>> chip B chan 2 lane 0 no good taps found
>> chip B chan 2 lane 1 no good taps found
>> chip B chan 3 lane 0 no good taps found
>> chip B chan 3 lane 1 no good taps found
>> chip B chan 4 lane 0 no good taps found
>> chip B chan 4 lane 1 no good taps found
>> chip C chan 1 lane 0 no good taps found
>> chip C chan 1 lane 1 no good taps found
>> chip C chan 2 lane 0 no good taps found
>> chip C chan 2 lane 1 no good taps found
>> chip C chan 3 lane 0 no good taps found
>> chip C chan 3 lane 1 no good taps found
>> chip C chan 4 lane 0 no good taps found
>> chip C chan 4 lane 1 no good taps found
>> chip D chan 1 lane 0 no good taps found
>> chip D chan 1 lane 1 no good taps found
>> chip D chan 2 lane 0 no good taps found
>> chip D chan 2 lane 1 no good taps found
>> chip D chan 3 lane 0 no good taps found
>> chip D chan 3 lane 1 no good taps found
>> chip D chan 4 lane 0 no good taps found
>> chip D chan 4 lane 1 no good taps found
>>
>> ERROR: SERDES calibration failed for ADC A.
>> ERROR: SERDES calibration failed for ADC B.
>> ERROR: SERDES calibration failed for ADC C.
>> ERROR: SERDES calibration failed for ADC D.
>> Selecting analog inputs...
>> Using default digital gain of 1...
>> Done!
>>
>>
>> On Wed, Mar 29, 2017 at 5:33 PM, Jack Hickish 
>> wrote:
>>
>> Further, is the board clocking OK? -- I believe the initialization script
>> should give feedback on whether of not the FPGA's PLL has successfully
>> locked to the ADC clock, and what the current measured board clock is.
>>
>> Cheers
>> Jack
>>
>> On Wed, 29 Mar 2017 at 14:28 Matt Dexter  wrote:
>>
>> Is the design and lab setup consistent with the limitations documented at
>> https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_
>> Rate_vs_Virtex-6_MMCM_Limitations
>> ?
>>
>> More information on the clock requirements may be found at
>> https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#
>> ADC16x250-8_coax_rev_2_Inputs
>>
>> Matt
>>
>> On Wed, 29 Mar 2017, vijay kumar wrote:
>>
>> > Date: Wed, 29 Mar 2017 17:16:34 -0400
>> > From: vijay kumar 
>> > To: casper@lists.berkeley.edu
>> > Subject: [casper] ADC calibration issue
>> >
>> > Hello Casperites,
>> > I have been working on the ROACH-2 casper for the past few months. Now
>> i have started to capture values from the ADC
>> > 16x250-8 block. But, when I am trying to run the initialization script,
>> it gives me an error saying that "chip 'x'
>> > chan 'x' lane 'x' no good taps found  ". I am unable to figure out what
>> might be causing this error. I would be glad
>> > if I could get help from you guys.
>> >
>> > Thank you.
>> >
>> >
>> > With regards
>> > Vijay
>> >
>> > --
>> > You received this message because you are subscribed to the Google
>> Groups "casper@lists.berkeley.edu" group.
>> > To unsubscribe from this group and stop receiving emails from it, send
>> an email to
>> > casper+unsubscr...@lists.berkeley.edu.
>> > To post to this group, send email to casper@lists.berkeley.edu.
>> >
>> >
>>
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Re: [casper] ADC calibration issue

2017-03-29 Thread Jack Hickish 
I like the triumphant "done!" at the end :)

Next questions --
What version of the adc repo and mlib_devel repos are you using?
Do you have other hardware you can test on? (It's very unlikely to be a
hardware problem, IMO, but worth checking if you can).
What ADC clock rate are you using?

Cheers
Jack

On Wed, 29 Mar 2017 at 14:39 vijay kumar 
wrote:

> Yes ! I assume the clock has been clocked. For convenience, I have
> included the output script i get after I run the initialization script.
>
>
> Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz...
> Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2)
> Gateware supports demux modes (using demux by 1)
> Resetting ADC, power cycling ADC, and reprogramming FPGA...
> ZDOK0 clock OK
> Calibrating SERDES blocks...calibrating chips ["A", "B", "C", "D"]
> chip A chan 1 lane 0 no good taps found
> chip A chan 1 lane 1 no good taps found
> chip A chan 2 lane 0 no good taps found
> chip A chan 2 lane 1 no good taps found
> chip A chan 3 lane 0 no good taps found
> chip A chan 3 lane 1 no good taps found
> chip A chan 4 lane 0 no good taps found
> chip A chan 4 lane 1 no good taps found
> chip B chan 1 lane 0 no good taps found
> chip B chan 1 lane 1 no good taps found
> chip B chan 2 lane 0 no good taps found
> chip B chan 2 lane 1 no good taps found
> chip B chan 3 lane 0 no good taps found
> chip B chan 3 lane 1 no good taps found
> chip B chan 4 lane 0 no good taps found
> chip B chan 4 lane 1 no good taps found
> chip C chan 1 lane 0 no good taps found
> chip C chan 1 lane 1 no good taps found
> chip C chan 2 lane 0 no good taps found
> chip C chan 2 lane 1 no good taps found
> chip C chan 3 lane 0 no good taps found
> chip C chan 3 lane 1 no good taps found
> chip C chan 4 lane 0 no good taps found
> chip C chan 4 lane 1 no good taps found
> chip D chan 1 lane 0 no good taps found
> chip D chan 1 lane 1 no good taps found
> chip D chan 2 lane 0 no good taps found
> chip D chan 2 lane 1 no good taps found
> chip D chan 3 lane 0 no good taps found
> chip D chan 3 lane 1 no good taps found
> chip D chan 4 lane 0 no good taps found
> chip D chan 4 lane 1 no good taps found
>
> ERROR: SERDES calibration failed for ADC A.
> ERROR: SERDES calibration failed for ADC B.
> ERROR: SERDES calibration failed for ADC C.
> ERROR: SERDES calibration failed for ADC D.
> Selecting analog inputs...
> Using default digital gain of 1...
> Done!
>
>
> On Wed, Mar 29, 2017 at 5:33 PM, Jack Hickish 
> wrote:
>
> Further, is the board clocking OK? -- I believe the initialization script
> should give feedback on whether of not the FPGA's PLL has successfully
> locked to the ADC clock, and what the current measured board clock is.
>
> Cheers
> Jack
>
> On Wed, 29 Mar 2017 at 14:28 Matt Dexter  wrote:
>
> Is the design and lab setup consistent with the limitations documented at
>
> https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Rate_vs_Virtex-6_MMCM_Limitations
> ?
>
> More information on the clock requirements may be found at
>
> https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#ADC16x250-8_coax_rev_2_Inputs
>
> Matt
>
> On Wed, 29 Mar 2017, vijay kumar wrote:
>
> > Date: Wed, 29 Mar 2017 17:16:34 -0400
> > From: vijay kumar 
> > To: casper@lists.berkeley.edu
> > Subject: [casper] ADC calibration issue
> >
> > Hello Casperites,
> > I have been working on the ROACH-2 casper for the past few months. Now i
> have started to capture values from the ADC
> > 16x250-8 block. But, when I am trying to run the initialization script,
> it gives me an error saying that "chip 'x'
> > chan 'x' lane 'x' no good taps found  ". I am unable to figure out what
> might be causing this error. I would be glad
> > if I could get help from you guys.
> >
> > Thank you.
> >
> >
> > With regards
> > Vijay
> >
> > --
> > You received this message because you are subscribed to the Google
> Groups "casper@lists.berkeley.edu" group.
> > To unsubscribe from this group and stop receiving emails from it, send
> an email to
> > casper+unsubscr...@lists.berkeley.edu.
> > To post to this group, send email to casper@lists.berkeley.edu.
> >
> >
>
> --
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> casper@lists.berkeley.edu" group.
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To

Re: [casper] ADC calibration issue

2017-03-29 Thread vijay kumar 
Yes ! I assume the clock has been clocked. For convenience, I have included
the output script i get after I run the initialization script.


Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz...
Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2)
Gateware supports demux modes (using demux by 1)
Resetting ADC, power cycling ADC, and reprogramming FPGA...
ZDOK0 clock OK
Calibrating SERDES blocks...calibrating chips ["A", "B", "C", "D"]
chip A chan 1 lane 0 no good taps found
chip A chan 1 lane 1 no good taps found
chip A chan 2 lane 0 no good taps found
chip A chan 2 lane 1 no good taps found
chip A chan 3 lane 0 no good taps found
chip A chan 3 lane 1 no good taps found
chip A chan 4 lane 0 no good taps found
chip A chan 4 lane 1 no good taps found
chip B chan 1 lane 0 no good taps found
chip B chan 1 lane 1 no good taps found
chip B chan 2 lane 0 no good taps found
chip B chan 2 lane 1 no good taps found
chip B chan 3 lane 0 no good taps found
chip B chan 3 lane 1 no good taps found
chip B chan 4 lane 0 no good taps found
chip B chan 4 lane 1 no good taps found
chip C chan 1 lane 0 no good taps found
chip C chan 1 lane 1 no good taps found
chip C chan 2 lane 0 no good taps found
chip C chan 2 lane 1 no good taps found
chip C chan 3 lane 0 no good taps found
chip C chan 3 lane 1 no good taps found
chip C chan 4 lane 0 no good taps found
chip C chan 4 lane 1 no good taps found
chip D chan 1 lane 0 no good taps found
chip D chan 1 lane 1 no good taps found
chip D chan 2 lane 0 no good taps found
chip D chan 2 lane 1 no good taps found
chip D chan 3 lane 0 no good taps found
chip D chan 3 lane 1 no good taps found
chip D chan 4 lane 0 no good taps found
chip D chan 4 lane 1 no good taps found

ERROR: SERDES calibration failed for ADC A.
ERROR: SERDES calibration failed for ADC B.
ERROR: SERDES calibration failed for ADC C.
ERROR: SERDES calibration failed for ADC D.
Selecting analog inputs...
Using default digital gain of 1...
Done!


On Wed, Mar 29, 2017 at 5:33 PM, Jack Hickish  wrote:

> Further, is the board clocking OK? -- I believe the initialization script
> should give feedback on whether of not the FPGA's PLL has successfully
> locked to the ADC clock, and what the current measured board clock is.
>
> Cheers
> Jack
>
> On Wed, 29 Mar 2017 at 14:28 Matt Dexter  wrote:
>
>> Is the design and lab setup consistent with the limitations documented at
>> https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_
>> Rate_vs_Virtex-6_MMCM_Limitations
>> ?
>>
>> More information on the clock requirements may be found at
>> https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#
>> ADC16x250-8_coax_rev_2_Inputs
>>
>> Matt
>>
>> On Wed, 29 Mar 2017, vijay kumar wrote:
>>
>> > Date: Wed, 29 Mar 2017 17:16:34 -0400
>> > From: vijay kumar 
>> > To: casper@lists.berkeley.edu
>> > Subject: [casper] ADC calibration issue
>> >
>> > Hello Casperites,
>> > I have been working on the ROACH-2 casper for the past few months. Now
>> i have started to capture values from the ADC
>> > 16x250-8 block. But, when I am trying to run the initialization script,
>> it gives me an error saying that "chip 'x'
>> > chan 'x' lane 'x' no good taps found  ". I am unable to figure out what
>> might be causing this error. I would be glad
>> > if I could get help from you guys.
>> >
>> > Thank you.
>> >
>> >
>> > With regards
>> > Vijay
>> >
>> > --
>> > You received this message because you are subscribed to the Google
>> Groups "casper@lists.berkeley.edu" group.
>> > To unsubscribe from this group and stop receiving emails from it, send
>> an email to
>> > casper+unsubscr...@lists.berkeley.edu.
>> > To post to this group, send email to casper@lists.berkeley.edu.
>> >
>> >
>>
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Re: [casper] ADC calibration issue

2017-03-29 Thread Jack Hickish 
Further, is the board clocking OK? -- I believe the initialization script
should give feedback on whether of not the FPGA's PLL has successfully
locked to the ADC clock, and what the current measured board clock is.

Cheers
Jack

On Wed, 29 Mar 2017 at 14:28 Matt Dexter  wrote:

> Is the design and lab setup consistent with the limitations documented at
>
> https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Rate_vs_Virtex-6_MMCM_Limitations
> ?
>
> More information on the clock requirements may be found at
>
> https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#ADC16x250-8_coax_rev_2_Inputs
>
> Matt
>
> On Wed, 29 Mar 2017, vijay kumar wrote:
>
> > Date: Wed, 29 Mar 2017 17:16:34 -0400
> > From: vijay kumar 
> > To: casper@lists.berkeley.edu
> > Subject: [casper] ADC calibration issue
> >
> > Hello Casperites,
> > I have been working on the ROACH-2 casper for the past few months. Now i
> have started to capture values from the ADC
> > 16x250-8 block. But, when I am trying to run the initialization script,
> it gives me an error saying that "chip 'x'
> > chan 'x' lane 'x' no good taps found  ". I am unable to figure out what
> might be causing this error. I would be glad
> > if I could get help from you guys.
> >
> > Thank you.
> >
> >
> > With regards
> > Vijay
> >
> > --
> > You received this message because you are subscribed to the Google
> Groups "casper@lists.berkeley.edu" group.
> > To unsubscribe from this group and stop receiving emails from it, send
> an email to
> > casper+unsubscr...@lists.berkeley.edu.
> > To post to this group, send email to casper@lists.berkeley.edu.
> >
> >
>
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Re: [casper] ADC calibration issue

2017-03-29 Thread Matt Dexter 

Is the design and lab setup consistent with the limitations documented at
https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Rate_vs_Virtex-6_MMCM_Limitations
?

More information on the clock requirements may be found at
https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#ADC16x250-8_coax_rev_2_Inputs

Matt

On Wed, 29 Mar 2017, vijay kumar wrote:


Date: Wed, 29 Mar 2017 17:16:34 -0400
From: vijay kumar 
To: casper@lists.berkeley.edu
Subject: [casper] ADC calibration issue

Hello Casperites,
I have been working on the ROACH-2 casper for the past few months. Now i have 
started to capture values from the ADC
16x250-8 block. But, when I am trying to run the initialization script, it gives me 
an error saying that "chip 'x'
chan 'x' lane 'x' no good taps found  ". I am unable to figure out what might 
be causing this error. I would be glad
if I could get help from you guys.

Thank you.


With regards
Vijay

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