from:"Florian Eckert"

[PATCH 1/1] platform/x86: revert pcengines-apuv2 wire up simswitch gpio as led

2020-07-13 Thread Florian Eckert

This reverts commit 5037d4ddda31c2dbbb018109655f61054b1756dc.

Explanation why this does not work:
This change connects the simswap to the LED subsystem of the kernel.
>From my point of view, it's nonsense. If we do it this way, then this
can be switched relatively easily via the LED subsystem (trigger:
none/default-on) and that is dangerous! If this is used, it would be
unfavorable, since there is also another trigger (trigger:
heartbeat/netdev).

Therefore, this simswap GPIO should remain in the GPIO
subsystem and be switched via it and not be connected to the LED
subsystem. To avoid the problems mentioned above. The LED subsystem is
not made for this and it is not a good compromise, but rather dangerous.

Signed-off-by: Florian Eckert 
---
 drivers/platform/x86/pcengines-apuv2.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/platform/x86/pcengines-apuv2.c 
b/drivers/platform/x86/pcengines-apuv2.c
index 9b11ef1a401f..6aff6cf41414 100644
--- a/drivers/platform/x86/pcengines-apuv2.c
+++ b/drivers/platform/x86/pcengines-apuv2.c
@@ -78,7 +78,6 @@ static const struct gpio_led apu2_leds[] = {
{ .name = "apu:green:1" },
{ .name = "apu:green:2" },
{ .name = "apu:green:3" },
-   { .name = "apu:simswap" },
 };
 
 static const struct gpio_led_platform_data apu2_leds_pdata = {
@@ -95,8 +94,6 @@ static struct gpiod_lookup_table gpios_led_table = {
NULL, 1, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX(AMD_FCH_GPIO_DRIVER_NAME, APU2_GPIO_LINE_LED3,
NULL, 2, GPIO_ACTIVE_LOW),
-   GPIO_LOOKUP_IDX(AMD_FCH_GPIO_DRIVER_NAME, 
APU2_GPIO_LINE_SIMSWAP,
-   NULL, 3, GPIO_ACTIVE_LOW),
}
 };
 
-- 
2.20.1

[PATCH v2 1/1] platform/x86/pcengines-apuv2: add mpcie reset gpio export

2019-07-26 Thread Florian Eckert

On APUx we have also mpcie2/mpcie3 reset pins. To make it possible to reset
the ports from the userspace, add the definition to this platform
device. The gpio can then be exported by the legancy gpio subsystem to
toggle the mpcie reset pin.

Signed-off-by: Florian Eckert 
---

v2:
  Noting changed for this patch. Only resend because other patches of
  the series where dropped or updated and resend by other people

 drivers/platform/x86/pcengines-apuv2.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/platform/x86/pcengines-apuv2.c 
b/drivers/platform/x86/pcengines-apuv2.c
index c1ca931e1fab..f6d8ed100cab 100644
--- a/drivers/platform/x86/pcengines-apuv2.c
+++ b/drivers/platform/x86/pcengines-apuv2.c
@@ -32,6 +32,8 @@
 #define APU2_GPIO_REG_LED3 AMD_FCH_GPIO_REG_GPIO59_DEVSLP1
 #define APU2_GPIO_REG_MODESW   AMD_FCH_GPIO_REG_GPIO32_GE1
 #define APU2_GPIO_REG_SIMSWAP  AMD_FCH_GPIO_REG_GPIO33_GE2
+#define APU2_GPIO_REG_MPCIE2   AMD_FCH_GPIO_REG_GPIO59_DEVSLP0
+#define APU2_GPIO_REG_MPCIE3   AMD_FCH_GPIO_REG_GPIO51
 
 /* order in which the gpio lines are defined in the register list */
 #define APU2_GPIO_LINE_LED10
@@ -39,6 +41,8 @@
 #define APU2_GPIO_LINE_LED32
 #define APU2_GPIO_LINE_MODESW  3
 #define APU2_GPIO_LINE_SIMSWAP 4
+#define APU2_GPIO_LINE_MPCIE2  5
+#define APU2_GPIO_LINE_MPCIE3  6
 
 /* gpio device */
 
@@ -48,6 +52,8 @@ static int apu2_gpio_regs[] = {
[APU2_GPIO_LINE_LED3]   = APU2_GPIO_REG_LED3,
[APU2_GPIO_LINE_MODESW] = APU2_GPIO_REG_MODESW,
[APU2_GPIO_LINE_SIMSWAP]= APU2_GPIO_REG_SIMSWAP,
+   [APU2_GPIO_LINE_MPCIE2] = APU2_GPIO_REG_MPCIE2,
+   [APU2_GPIO_LINE_MPCIE3] = APU2_GPIO_REG_MPCIE3,
 };
 
 static const char * const apu2_gpio_names[] = {
@@ -56,6 +62,8 @@ static const char * const apu2_gpio_names[] = {
[APU2_GPIO_LINE_LED3]   = "front-led3",
[APU2_GPIO_LINE_MODESW] = "front-button",
[APU2_GPIO_LINE_SIMSWAP]= "simswap",
+   [APU2_GPIO_LINE_MPCIE2] = "mpcie2_reset",
+   [APU2_GPIO_LINE_MPCIE3] = "mpcie3_reset",
 };
 
 static const struct amd_fch_gpio_pdata board_apu2 = {
-- 
2.11.0

Re: [PATCH 3/3] platform//x86/pcengines-apuv2: update gpio button definition

2019-07-23 Thread Florian Eckert

> I'd like to ack only the keycode change, but not the deprecated .gpio
> field. I'll post a separate patch for the keycode change only.

I am fine if we only change the keycode.
Do I have to send a v2 patch set?

Re: [PATCH 1/3] platform/x86/pcengines-apuv2: add mpcie reset gpio export

2019-07-15 Thread Florian Eckert




On APUx we have also mpcie2/mpcie3 reset pins. To make it possible to 
reset

the ports from the userspace, add the definition to this platform
device. The gpio can then be exported by the legancy gpio subsystem to
toggle the mpcie reset pin.



Just tested your patch on an apu3. The driver itself seems to work,
but the pins don't seem to actually do anything.

How exactly did you test it ? Do you have some test case ?


I plugged in a mpcie  usb modem.
In my test case it was a EC25 from Quectel in mpcie2 port.
After that I did a reboot and exported the gpio via "/sys/class/gpio"
Then I executed the command "echo 0 > /sys/class/gpio//value" and 
"echo 1 > /sys/class/gpio//value".
Then I have seen the log message in the kernel that the device did an 
unregistration/registration

.
-- Florian

Re: [PATCH 0/3] Update pcengines-apuv2 platform device

2019-07-10 Thread Florian Eckert


On 2019-07-08 21:45, Enrico Weigelt, metux IT consult wrote:

On 04.07.19 15:39, Andy Shevchenko wrote:

On Thu, Jul 4, 2019 at 12:02 PM Florian Eckert  wrote:


This patchset adds the following changes to this pcengines-apuv2
platform device.



Before doing anything to this driver, what is the plan for previously
upstreamed:

drivers/leds/leds-apu.c


Only supports the three front LEDs, nothing else. (we've got more gpios
that are not LEDs, eg. the front button, simsw, ...)


arch/x86/platform/geode/alix.c


completely unrelated - very different chipset.


--mtx


I'm going to sum it all what we have

ALIX family boards (https://www.pcengines.ch/alix.htm):
CPU -> AMD Geode LX CPU
Stays as it is different because it has a different CPU

APU family boards (https://www.pcengines.ch/apu.htm):
CPU -> AMD G series T40E APU
Remove the related APU2 family stuff from the LEDs driver
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/leds/leds-apu.c
this will be handled in the future by the platform device
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/platform/x86/pcengines-apuv2.c
The other GPIOs are not supported by this platform. Only LEDs are 
supported for now.


APU2 family boards (https://www.pcengines.ch/apu2.htm):
CPU -> AMD Embedded G series GX-412TC
Add the additional mpcie reset pins and add additional board 
descriptions to

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/platform/x86/pcengines-apuv2.c?h=v5.2#n61
so we can distinguish between the APU2,APU3 and APU4 boards of the APU2 
board family.


My research in the pcengines documentation shows the following GPIO pins 
for the individual boards which we can support.


APU2:
front-led1
front-led2
front-led3
front-button
mpcie2_reset
mpcie3_reset

APU3:
front-led1
front-led2
front-led3
front-button
mpcie2_reset
mpcie3_reset
simswap

APU4:
front-led1
front-led2
front-led3
front-button
mpcie2_reset
mpcie3_reset

Until now we support aAPU2 and APU3 and treat it the same way. But the 
APU2 does not have a simswap.


Kind regards

Florian

Re: [PATCH 1/3] platform/x86/pcengines-apuv2: add mpcie reset gpio export

2019-07-10 Thread Florian Eckert


On 2019-07-08 21:44, Enrico Weigelt, metux IT consult wrote:

On 04.07.19 11:02, Florian Eckert wrote:
On APUx we have also mpcie2/mpcie3 reset pins. To make it possible to 
reset

the ports from the userspace, add the definition to this platform
device. The gpio can then be exported by the legancy gpio subsystem to
toggle the mpcie reset pin.


Are you sure they're also available on APUv2 (not just v3) ?


We have the following models on APU2 family:
The schematic could be downloaded for all APU2 family boards from this 
side.

See https://www.pcengines.ch/apu2.htm

They all use the similar PCB with some minimal changes.

APU2
2 mpcie slot
apu2d0 (2 GB DRAM, 2 i211AT NICs)
apu2d2 (2 GB DRAM, 3 i211AT NICs)
apu2d4 (4 GB DRAM, 3 i210AT NICs)

J14 (USB + SIM1) PE3_RST to GPIO G51
J13 (USB + SIM2) PE4_RST to GPIO G55

APU3
3 mpcie slot
apu3c2 (2 GB DRAM, 3 i211AT NICs, optimized for 3G/LTE modems)
apu3c4 (4 GB DRAM, 3 i211AT NICs, optimized for 3G/LTE modems)

J16 (PCIe + USB no SIM) not connected to a userland GPIO
J15 (USB SIM1) PE4_RST to GPIO G55
J14 (mSATA or USB SIM2) PE3_RST to GPIO G51

APU4
3 mpcie slot
apu4c2 (2 GB DRAM, 4 i211AT NICs)
apu4c4 (4 GB DRAM, 4 i211AT NICs)

J15 (PCIe + USB no SIM) not connected to a userland GPIO
J14 (USB SIM1) PE4_RST to GPIO G55
J13 (mSATA or USB SIM2) PE3_RST to GPIO G51

Please check again so that I have not done any mistake.

So all USB only mpcie slots could be reseted by a GPIO G51 and G55.

Kind regards

Flo

Re: [PATCH 2/3] platform/x86/pcengines-apuv2: add legacy leds gpio definitions

2019-07-10 Thread Florian Eckert


On 2019-07-08 21:42, Enrico Weigelt, metux IT consult wrote:

On 04.07.19 11:02, Florian Eckert wrote:

Extend the apu2_leds definition to make the leds exportable via the
legacy gpio subsystem.


What for ? The gpios are bound to LED devices as that's exactly what
they are: LEDs.


I have back ported your pcengines-apuv2 device and gpio-amd-fch GPIO 
driver to the kernel version 4.19 on OpenWrt.
If I compile and load this without the change no LEDs are visible in 
"/sys/class/leds"!


From my point of view the connection between the GPIO and the LEDs 
subsystem is missing.

How should the LED subsystem know which GPIO to use?
If I add the change to the pcengines-apuv2 device then the LEDs will be 
visilbe under "/sys/class/leds"

and could be used, by OpenWrt userland.

Mybe I miss something.

Re: [PATCH 0/3] Update pcengines-apuv2 platform device

2019-07-05 Thread Florian Eckert

Hello Andy

>> This patchset adds the following changes to this pcengines-apuv2
>> platform device.
>>
>
> Before doing anything to this driver, what is the plan for previously
> upstreamed:
>
> drivers/leds/leds-apu.c

I think we can remove the related APU2/APU3 code stuff from this
driver.

The recently added pcengines-apuv2 driver does *not* support the APU1.
So I think we need the related APU1 stuff if we still want to support
this board.

So, I would like to see some unification (since it's material for v5.4
cycle anyway, we have time).

A few thoughts and information about your suggestion to unify this.

APU1 (PC-Engines) CPU "AMD G series T40E APU":
This is also an old design and is not recommend for new design
(deprecated).

Also not many were produced and are in the field.
See https://pcengines.ch/apu.htm

Platform-Device (LEDs, Button):
I have no platform device description found in the linux sources.
So the GPIO button should not work.

LEDs-Driver:
Only the LEDs should work with this device driver.
This is shared additonal with new APU2/APU3.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/leds/leds-apu.c

I think we should remove the APU2/APU3 stuff. This will now be handled
by the new gpio-amd-fch.c / pcengines-apuv2.c

kombination.

APU2/APU3/APU4 (PC-Engines) CPU "AMD Embedded G series GX-412TC":
This is the newest design and is recommend for new products.
See https://pcengines.ch/apu2.htm

GPIO-Driver:
The following driver is responsible for the GPIO export and handling
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpio/gpio-amd-fch.c

Platform-Device (LEDs, Button):
This Platform description is only valid for APU2/APU3 and not for APU1.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/platform/x86/pcengines-apuv2.c

LEDs-Driver:
We have an additional device only for LEDs this works for
APU1/APU2/APU3.
I think we should remove the APU2/APU3 LEDs from the leds-apu device as
mentioned above.

So this device supports only the APU1 LEDs.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/leds/leds-apu.c

We could extend and/or rename the pcengienes-apuv2 device to support
also APU3 and the newest APU4.
The APU2 does only have LEDs Button and the MPCIE2 reset lines see my
patch.

The APU3 does have an additional the simswap pin.
So the current pcengines-apuv2 platform is from my point of view wrong.
We should change this to the following layout and add the legacy GPIO
numbering.

This are the following GPIOs:

APU2:
LED1
LED2
LED3
BUTTON
MPCIE2
MPCIE3

APU3:
LED1
LED2
LED3
BUTTON
MPCIE2
MPCIE3
SIMSWAP

APU4:
TODO

> arch/x86/platform/geode/alix.c

I think this is not related because this is a different platform
driver.

Maybe we should move them to drivers/platform/x86?

You mentioned somewhere ALIx, can you elaborate if these are platforms
of the same family (PC engines)?

Looking into the code, I think we may unify all three under umbrella
of one driver if the above is true.

ALIX (PC-Engines) CPU "AMD Geode LX":
This is an old design we have already in use and is not recommend for
new design (deprecated)

https://pcengines.ch/alix.htm

GPIO-Driver:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpio/gpio-cs5535.c

Platform-Device (LEDs, button):
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/platform/geode/alix.c

I think we should leave the driver as it is because this is a different
design and has nothing to do with the PUs.
The only thing I can imagine is to move the platform device to
"drivers/platform/x86", but this is cosmetic.
I have only mentioned the alix board to explain why I think that we
should change the APU key code from the GPIO button to unify this.

With Best Regards,

Florian

Re: [PATCH 0/3] Update pcengines-apuv2 platform device

2019-07-04 Thread Florian Eckert


Hello Andy,

thanks for feedback


This patchset adds the following changes to this pcengines-apuv2
platform device.



Before doing anything to this driver, what is the plan for previously
upstreamed:

drivers/leds/leds-apu.c


I think we can remove the related APU2/APU3 code stuff from this driver.
The recently added pcengines-apuv2 driver does *not* support the APU1.
So I think we need the related APU1 stuff if we still want to support 
this board.



arch/x86/platform/geode/alix.c


I think this is not related because this is a different platform driver.
Maybe we should move them to drivers/platform/x86?

Regards

Florian

[PATCH 0/3] Update pcengines-apuv2 platform device

2019-07-04 Thread Florian Eckert

This patchset adds the following changes to this pcengines-apuv2
platform device.

* Add mpcie reset gpio export
* Add legacy leds gpio definitions
* Update gpio buttion definitions

Florian Eckert (3):
  platform/x86/pcengines-apuv2: add mpcie reset gpio export
  platform/x86/pcengines-apuv2: add legacy leds gpio definitions
  platform//x86/pcengines-apuv2: update gpio button definition

 drivers/platform/x86/pcengines-apuv2.c | 32 
 1 file changed, 28 insertions(+), 4 deletions(-)

-- 
2.11.0

[PATCH 3/3] platform//x86/pcengines-apuv2: update gpio button definition

2019-07-04 Thread Florian Eckert

* Add the gpio number, so the button subsystem can find the right gpio.
* Change also the keycode from KEY_SETUP to KEY_RESTART, because it
  seems more expressive to me and in the Alix-Board, which is the
  predecessor, there isthis keycode defined too. I think this is also
  intended by Pcengines. Also many embedded systems defined in the kernel
  use this key code as well.

Signed-off-by: Florian Eckert 
---
 drivers/platform/x86/pcengines-apuv2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/platform/x86/pcengines-apuv2.c 
b/drivers/platform/x86/pcengines-apuv2.c
index d50a50e9d34c..370fd2686d59 100644
--- a/drivers/platform/x86/pcengines-apuv2.c
+++ b/drivers/platform/x86/pcengines-apuv2.c
@@ -116,7 +116,8 @@ struct gpiod_lookup_table gpios_led_table = {
 
 static struct gpio_keys_button apu2_keys_buttons[] = {
{
-   .code   = KEY_SETUP,
+   .code   = KEY_RESTART,
+   .gpio   = 508,
.active_low = 1,
.desc   = "front button",
.type   = EV_KEY,
-- 
2.11.0

[PATCH 1/3] platform/x86/pcengines-apuv2: add mpcie reset gpio export

2019-07-04 Thread Florian Eckert

On APUx we have also mpcie2/mpcie3 reset pins. To make it possible to reset
the ports from the userspace, add the definition to this platform
device. The gpio can then be exported by the legancy gpio subsystem to
toggle the mpcie reset pin.

Signed-off-by: Florian Eckert 
---
 drivers/platform/x86/pcengines-apuv2.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/platform/x86/pcengines-apuv2.c 
b/drivers/platform/x86/pcengines-apuv2.c
index c1ca931e1fab..f6d8ed100cab 100644
--- a/drivers/platform/x86/pcengines-apuv2.c
+++ b/drivers/platform/x86/pcengines-apuv2.c
@@ -32,6 +32,8 @@
 #define APU2_GPIO_REG_LED3 AMD_FCH_GPIO_REG_GPIO59_DEVSLP1
 #define APU2_GPIO_REG_MODESW   AMD_FCH_GPIO_REG_GPIO32_GE1
 #define APU2_GPIO_REG_SIMSWAP  AMD_FCH_GPIO_REG_GPIO33_GE2
+#define APU2_GPIO_REG_MPCIE2   AMD_FCH_GPIO_REG_GPIO59_DEVSLP0
+#define APU2_GPIO_REG_MPCIE3   AMD_FCH_GPIO_REG_GPIO51
 
 /* order in which the gpio lines are defined in the register list */
 #define APU2_GPIO_LINE_LED10
@@ -39,6 +41,8 @@
 #define APU2_GPIO_LINE_LED32
 #define APU2_GPIO_LINE_MODESW  3
 #define APU2_GPIO_LINE_SIMSWAP 4
+#define APU2_GPIO_LINE_MPCIE2  5
+#define APU2_GPIO_LINE_MPCIE3  6
 
 /* gpio device */
 
@@ -48,6 +52,8 @@ static int apu2_gpio_regs[] = {
[APU2_GPIO_LINE_LED3]   = APU2_GPIO_REG_LED3,
[APU2_GPIO_LINE_MODESW] = APU2_GPIO_REG_MODESW,
[APU2_GPIO_LINE_SIMSWAP]= APU2_GPIO_REG_SIMSWAP,
+   [APU2_GPIO_LINE_MPCIE2] = APU2_GPIO_REG_MPCIE2,
+   [APU2_GPIO_LINE_MPCIE3] = APU2_GPIO_REG_MPCIE3,
 };
 
 static const char * const apu2_gpio_names[] = {
@@ -56,6 +62,8 @@ static const char * const apu2_gpio_names[] = {
[APU2_GPIO_LINE_LED3]   = "front-led3",
[APU2_GPIO_LINE_MODESW] = "front-button",
[APU2_GPIO_LINE_SIMSWAP]= "simswap",
+   [APU2_GPIO_LINE_MPCIE2] = "mpcie2_reset",
+   [APU2_GPIO_LINE_MPCIE3] = "mpcie3_reset",
 };
 
 static const struct amd_fch_gpio_pdata board_apu2 = {
-- 
2.11.0

[PATCH 2/3] platform/x86/pcengines-apuv2: add legacy leds gpio definitions

2019-07-04 Thread Florian Eckert

Extend the apu2_leds definition to make the leds exportable via the
legacy gpio subsystem. Without this change the leds are not visible
under "/sys/class/leds" and could not be configured.

Signed-off-by: Florian Eckert 
---
 drivers/platform/x86/pcengines-apuv2.c | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/platform/x86/pcengines-apuv2.c 
b/drivers/platform/x86/pcengines-apuv2.c
index f6d8ed100cab..d50a50e9d34c 100644
--- a/drivers/platform/x86/pcengines-apuv2.c
+++ b/drivers/platform/x86/pcengines-apuv2.c
@@ -75,9 +75,24 @@ static const struct amd_fch_gpio_pdata board_apu2 = {
 /* gpio leds device */
 
 static const struct gpio_led apu2_leds[] = {
-   { .name = "apu:green:1" },
-   { .name = "apu:green:2" },
-   { .name = "apu:green:3" }
+   {
+   .name= "apu:green:1",
+   .gpio= 505,
+   .default_trigger = "default-off",
+   .active_low  = 1,
+   },
+   {
+   .name= "apu:green:2",
+   .gpio= 506,
+   .default_trigger = "default-off",
+   .active_low  = 1,
+   },
+   {
+   .name= "apu:green:3",
+   .gpio= 507,
+   .default_trigger = "default-off",
+   .active_low  = 1,
+   }
 };
 
 static const struct gpio_led_platform_data apu2_leds_pdata = {
-- 
2.11.0

Re: [PATCH v5 1/2] gpio: Add driver for PC Engines APU boards

2018-12-04 Thread Florian Eckert






/*
 * Multi-line comments
 * have this style
 */


fixed



+#include 


kbuild bot complains for absence of

#include 

here.



fixed

+static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int 
offset)

+{
+   u32 val;
+   struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+   spin_lock(_gpio->lock);
+



+   val = ~ioread32(apu_gpio->addr[offset]);


There is no need to do ~ under spin lock.



fixed


+
+   spin_unlock(_gpio->lock);
+
+   return !!(val & BIT(APU_GPIO_BIT_DIR));
+}



+   if (dmi_check_system(apu3_gpio_dmi_table)) {


(1)


+   apu_gpio->addr = devm_kzalloc(>dev,
+   sizeof(apu3_gpio_offset),
+   GFP_KERNEL);



+


No need to have this blank line. Same for the other cases.



fixed


+   if (!apu_gpio->addr)
+   return -ENOMEM;



+   } else if (dmi_check_system(apu2_gpio_dmi_table)) {


(2)

I think I have already told about (1) and (2). You may create two
callbacks and utilize .callback member in DMI table.



Done but I do not seen any advantage. I used the following driver as 
basis.

https://github.com/torvalds/linux/blob/master/drivers/leds/leds-clevo-mail.c


+   }



+static int __init apu_gpio_init(void)
+{



+   if (!(dmi_check_system(apu2_gpio_dmi_table)) &&
+   !(dmi_check_system(apu3_gpio_dmi_table))) {
+   pr_err("No PC Engines board detected\n");
+   return -ENODEV;
+   }


I don't think we need this.



see below



+}
+
+module_init(apu_gpio_init);
+module_exit(apu_gpio_exit);




After removing unneeded checks why not to simple use
module_platform_driver()
?


I have fixed all the above hints from you now but using 
"module_platform_driver" is no option.
I played around with them but the driver does not find any device. So I 
need the init function
to add a platform device. Only if I do this way driver and device will 
find and match. And I

see the gpios under /sys/class/gpio. So I think I need this?
I have not find any driver who has the same problems
I used the following drivers as my basis:
https://github.com/torvalds/linux/blob/master/drivers/leds/leds-apu.c
https://github.com/torvalds/linux/blob/master/drivers/leds/leds-clevo-mail.c
They all use dmi and need init/exit for platform device register and 
unregister

Re: [PATCH v5 1/2] gpio: Add driver for PC Engines APU boards

2018-12-04 Thread Florian Eckert






/*
 * Multi-line comments
 * have this style
 */


fixed



+#include 


kbuild bot complains for absence of

#include 

here.



fixed

+static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int 
offset)

+{
+   u32 val;
+   struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+   spin_lock(_gpio->lock);
+



+   val = ~ioread32(apu_gpio->addr[offset]);


There is no need to do ~ under spin lock.



fixed


+
+   spin_unlock(_gpio->lock);
+
+   return !!(val & BIT(APU_GPIO_BIT_DIR));
+}



+   if (dmi_check_system(apu3_gpio_dmi_table)) {


(1)


+   apu_gpio->addr = devm_kzalloc(>dev,
+   sizeof(apu3_gpio_offset),
+   GFP_KERNEL);



+


No need to have this blank line. Same for the other cases.



fixed


+   if (!apu_gpio->addr)
+   return -ENOMEM;



+   } else if (dmi_check_system(apu2_gpio_dmi_table)) {


(2)

I think I have already told about (1) and (2). You may create two
callbacks and utilize .callback member in DMI table.



Done but I do not seen any advantage. I used the following driver as 
basis.

https://github.com/torvalds/linux/blob/master/drivers/leds/leds-clevo-mail.c


+   }



+static int __init apu_gpio_init(void)
+{



+   if (!(dmi_check_system(apu2_gpio_dmi_table)) &&
+   !(dmi_check_system(apu3_gpio_dmi_table))) {
+   pr_err("No PC Engines board detected\n");
+   return -ENODEV;
+   }


I don't think we need this.



see below



+}
+
+module_init(apu_gpio_init);
+module_exit(apu_gpio_exit);




After removing unneeded checks why not to simple use
module_platform_driver()
?


I have fixed all the above hints from you now but using 
"module_platform_driver" is no option.
I played around with them but the driver does not find any device. So I 
need the init function
to add a platform device. Only if I do this way driver and device will 
find and match. And I

see the gpios under /sys/class/gpio. So I think I need this?
I have not find any driver who has the same problems
I used the following drivers as my basis:
https://github.com/torvalds/linux/blob/master/drivers/leds/leds-apu.c
https://github.com/torvalds/linux/blob/master/drivers/leds/leds-clevo-mail.c
They all use dmi and need init/exit for platform device register and 
unregister

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

2018-12-04 Thread Florian Eckert


>> Yes i will fix your hints tomorrow and send a v6 of my patchset.
>> Thank you for your hints and time
>> It would be nice if you could fix ACPI problemmatik.
>
> I would like to see the ACPI dump for that...

See 
https://github.com/openwrt/openwrt/pull/1232#issuecomment-443224576

In this comment Michał Żygowski appended to this thread the missing
files you want to have.



So, let me clarify what we have:
 - some platforms are in the wild with old BIOS with broken ACPI tables


correct

 - you still may fix the things for new BIOS version for all affected 
platforms


I have seen that this is a lot of work and I didn't think it was so 
complicated!

To get the GPIO support for APU2/APU3 merged into the gpio subsystem.
I am little confused what i should do now. By the way I only have one 
board (APU3).



 - you need to support both


That is not necessary from my point of view. I am fine if the driver 
supports at least
the current BIOS version. And if the coreboot maintainer fixes the ACPI 
problem

then we could extend the driver and add the ACPI stuff.
But this not in my hand, right?


For broken firmware you need to do the following:
 - create an MFD driver, which would instantiate GPIO and GPIO keys
support (at least)
 - create one of each above drivers w/o any DMI crap (should be done
as a part of MFD driver)


I will have a look how to achieve this.
If we want to support all BIOS version.
And is a must have to get the driver into mainline.


For fixed BIOS you need to add the following (example, not a fully
correct solution) at the level behind SB:


I do not understand how I could fix this. I have no idea from ACPI.
I have not found any driver where I can inspire myself.



Scope (SB)
{
  Device(GPIO)
  {



After updating firmware you would need just an ACPI ID table to be
added to the GPIO driver. MFD driver should not be enumerated at all.


That's maybe coming next when the coreboot maintainers have their bios 
fixed, right?

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

2018-12-04 Thread Florian Eckert


>> Yes i will fix your hints tomorrow and send a v6 of my patchset.
>> Thank you for your hints and time
>> It would be nice if you could fix ACPI problemmatik.
>
> I would like to see the ACPI dump for that...

See 
https://github.com/openwrt/openwrt/pull/1232#issuecomment-443224576

In this comment Michał Żygowski appended to this thread the missing
files you want to have.



So, let me clarify what we have:
 - some platforms are in the wild with old BIOS with broken ACPI tables


correct

 - you still may fix the things for new BIOS version for all affected 
platforms


I have seen that this is a lot of work and I didn't think it was so 
complicated!

To get the GPIO support for APU2/APU3 merged into the gpio subsystem.
I am little confused what i should do now. By the way I only have one 
board (APU3).



 - you need to support both


That is not necessary from my point of view. I am fine if the driver 
supports at least
the current BIOS version. And if the coreboot maintainer fixes the ACPI 
problem

then we could extend the driver and add the ACPI stuff.
But this not in my hand, right?


For broken firmware you need to do the following:
 - create an MFD driver, which would instantiate GPIO and GPIO keys
support (at least)
 - create one of each above drivers w/o any DMI crap (should be done
as a part of MFD driver)


I will have a look how to achieve this.
If we want to support all BIOS version.
And is a must have to get the driver into mainline.


For fixed BIOS you need to add the following (example, not a fully
correct solution) at the level behind SB:


I do not understand how I could fix this. I have no idea from ACPI.
I have not found any driver where I can inspire myself.



Scope (SB)
{
  Device(GPIO)
  {



After updating firmware you would need just an ACPI ID table to be
added to the GPIO driver. MFD driver should not be enumerated at all.


That's maybe coming next when the coreboot maintainers have their bios 
fixed, right?

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

2018-12-02 Thread Florian Eckert


Hello Andy


> Btw, is the statement in above email still actual? "...I can fix
> required things."



Yes i will fix your hints tomorrow and send a v6 of my patchset.
Thank you for your hints and time
It would be nice if you could fix ACPI problemmatik.


I would like to see the ACPI dump for that...


See https://github.com/openwrt/openwrt/pull/1232#issuecomment-443224576
In this comment Michał Żygowski appended to this thread the missing
files you want to have.

Regards
Flo

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

2018-12-02 Thread Florian Eckert


Hello Andy


> Btw, is the statement in above email still actual? "...I can fix
> required things."



Yes i will fix your hints tomorrow and send a v6 of my patchset.
Thank you for your hints and time
It would be nice if you could fix ACPI problemmatik.


I would like to see the ACPI dump for that...


See https://github.com/openwrt/openwrt/pull/1232#issuecomment-443224576
In this comment Michał Żygowski appended to this thread the missing
files you want to have.

Regards
Flo

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

2018-11-29 Thread Florian Eckert


Thank you very very much for your code review "again" I will update my
patch set with your hints.
Should I send v6 or should i wait till I get feedback from you about
ACPI?

>>
>> Until now it was not possible to get more information to detect the
>> MMIO_BASE address from the ACPI subsystem.
>
> I'm sorry if I already asked, please, remind me where dump of ACPI
> tables can be found?

https://www.spinics.net/lists/kernel/msg2887290.html


Unfortunately the file had been removed.

Btw, is the statement in above email still actual? "...I can fix
required things."



Yes i will fix your hints tomorrow and send a v6 of my patchset.
Thank you for your hints and time
It would be nice if you could fix ACPI problemmatik.

Best regards
Florian Eckert

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

2018-11-29 Thread Florian Eckert


Thank you very very much for your code review "again" I will update my
patch set with your hints.
Should I send v6 or should i wait till I get feedback from you about
ACPI?

>>
>> Until now it was not possible to get more information to detect the
>> MMIO_BASE address from the ACPI subsystem.
>
> I'm sorry if I already asked, please, remind me where dump of ACPI
> tables can be found?

https://www.spinics.net/lists/kernel/msg2887290.html


Unfortunately the file had been removed.

Btw, is the statement in above email still actual? "...I can fix
required things."



Yes i will fix your hints tomorrow and send a v6 of my patchset.
Thank you for your hints and time
It would be nice if you could fix ACPI problemmatik.

Best regards
Florian Eckert

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

2018-11-29 Thread Florian Eckert


Hello Andy,

Thank you very very much for your code review "again" I will update my 
patch set with your hints.
Should I send v6 or should i wait till I get feedback from you about 
ACPI?




Until now it was not possible to get more information to detect the
MMIO_BASE address from the ACPI subsystem.


I'm sorry if I already asked, please, remind me where dump of ACPI
tables can be found?


https://www.spinics.net/lists/kernel/msg2887290.html

Also would be nice to have the output of `lspci -nk -vv -xxx` on such 
platform.


00:00.0 0600: 1022:1566
Subsystem: 1022:1566
	Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- 
Latency: 0
lspci: Unable to load libkmod resources: error -12
00: 22 10 66 15 04 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 66 15
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00
50: 22 10 66 15 00 00 00 00 00 00 00 00 00 00 00 00
60: 46 00 00 00 63 10 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00
80: 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 7f 2c 00 00 00 02 02 19 00 00 00 00 00
a0: 01 80 30 01 ef be ad de 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 04 00 10 c2 03 00 00 00
c0: 00 00 00 00 00 00 00 00 01 00 12 00 00 00 14 00
d0: b6 14 30 01 00 00 00 00 00 00 00 00 00 00 00 00
e0: 10 00 40 01 01 11 e3 80 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 80 80 00 00 00 00 00 05 00 00 00

00:02.0 0600: 1022:156b
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- 
00: 22 10 6b 15 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.2 0604: 1022:1439 (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- 
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin B routed to IRQ 24
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 1000-1fff [size=4K]
Memory behind bridge: fe50-fe5f [size=1M]
Prefetchable memory behind bridge: None
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- 
BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA 
PME(D0+,D1-,D2-,D3hot+,D3cold+)

Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- 
Unsupported-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 256 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- 
TransPend-
		LnkCap:	Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s 
<512ns, L1 <64us

ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ 
BWMgmt+ ABWMgmt-

SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- 
Surprise-
Slot #0, PowerLimit 0.000W; Interlock- NoCompl+
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- 
LinkChg-

Control: AttnInd Unknown, PwrInd Unknown, Power- 
Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ 
Interlock-
Changed: MRL- PresDet+ LinkState+
		RootCtl: ErrCorrectable-

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

2018-11-29 Thread Florian Eckert


Hello Andy,

Thank you very very much for your code review "again" I will update my 
patch set with your hints.
Should I send v6 or should i wait till I get feedback from you about 
ACPI?




Until now it was not possible to get more information to detect the
MMIO_BASE address from the ACPI subsystem.


I'm sorry if I already asked, please, remind me where dump of ACPI
tables can be found?


https://www.spinics.net/lists/kernel/msg2887290.html

Also would be nice to have the output of `lspci -nk -vv -xxx` on such 
platform.


00:00.0 0600: 1022:1566
Subsystem: 1022:1566
	Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- 
Latency: 0
lspci: Unable to load libkmod resources: error -12
00: 22 10 66 15 04 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 66 15
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00
50: 22 10 66 15 00 00 00 00 00 00 00 00 00 00 00 00
60: 46 00 00 00 63 10 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00
80: 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 7f 2c 00 00 00 02 02 19 00 00 00 00 00
a0: 01 80 30 01 ef be ad de 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 04 00 10 c2 03 00 00 00
c0: 00 00 00 00 00 00 00 00 01 00 12 00 00 00 14 00
d0: b6 14 30 01 00 00 00 00 00 00 00 00 00 00 00 00
e0: 10 00 40 01 01 11 e3 80 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 80 80 00 00 00 00 00 05 00 00 00

00:02.0 0600: 1022:156b
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- 
00: 22 10 6b 15 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.2 0604: 1022:1439 (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- 
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin B routed to IRQ 24
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 1000-1fff [size=4K]
Memory behind bridge: fe50-fe5f [size=1M]
Prefetchable memory behind bridge: None
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- 
BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA 
PME(D0+,D1-,D2-,D3hot+,D3cold+)

Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- 
Unsupported-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 256 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- 
TransPend-
		LnkCap:	Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s 
<512ns, L1 <64us

ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ 
BWMgmt+ ABWMgmt-

SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- 
Surprise-
Slot #0, PowerLimit 0.000W; Interlock- NoCompl+
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- 
LinkChg-

Control: AttnInd Unknown, PwrInd Unknown, Power- 
Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ 
Interlock-
Changed: MRL- PresDet+ LinkState+
		RootCtl: ErrCorrectable-

[PATCH v5 1/2] gpio: Add driver for PC Engines APU boards

2018-11-27 Thread Florian Eckert

Add a new device driver "gpio-apu" which will handle the GPIOs on APU2
and APU3 devices from PC Engines.

APU2 (https://pcengines.ch/schema/apu2c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line

APU3 (https://pcengines.ch/schema/apu3c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line
- G33 is "simswap" connected to SIM switch IC to swap the SIM between
  mPCIe2 and mPCIe3 slot

Signed-off-by: Florian Eckert 
---
 drivers/gpio/Kconfig|   7 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/gpio-apu.c | 288 
 3 files changed, 296 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 833a1b51c948..e89937f6051e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -117,6 +117,13 @@ config GPIO_AMDPT
  driver for GPIO functionality on Promontory IOHub
  Require ACPI ASL code to enumerate as a platform device.
 
+config GPIO_APU
+   tristate "PC Engines APU2/APU3 GPIO support"
+   depends on X86
+   help
+ Say Y here to support GPIO functionality on APU2/APU3 boards
+ from PC Engines.
+
 config GPIO_ASPEED
tristate "Aspeed GPIO support"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 671c4477c951..9c27523fb189 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
 obj-$(CONFIG_GPIO_ALTERA_A10SR)+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)   += gpio-amdpt.o
+obj-$(CONFIG_GPIO_APU) += gpio-apu.o
 obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
 obj-$(CONFIG_GPIO_ATH79)   += gpio-ath79.o
 obj-$(CONFIG_GPIO_ASPEED)  += gpio-aspeed.o
diff --git a/drivers/gpio/gpio-apu.c b/drivers/gpio/gpio-apu.c
new file mode 100644
index ..609972d11847
--- /dev/null
+++ b/drivers/gpio/gpio-apu.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0
+/* PC Engines APU2/APU3 GPIO device driver
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)
+#define APU_GPIO_BIT_RD16
+#define APU_GPIO_BIT_WR22
+#define APU_GPIO_BIT_DIR   23
+
+struct apu_gpio_pdata {
+   struct gpio_chip chip;
+   unsigned long *offset;  /* base register offset */
+   void __iomem **addr;/* remapped iomem addresses */
+   spinlock_t lock;/* lock register access */
+};
+
+static struct platform_device *apu_gpio_pdev;
+
+/* APU2 */
+static unsigned long apu2_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+};
+static const char * const apu2_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+};
+
+/* APU3 */
+static unsigned long apu3_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 90 * sizeof(u32),
+};
+static const char * const apu3_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+   "simswap",
+};
+
+static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+   struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+   spin_lock(_gpio->lock);
+
+   val = ~ioread32(apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return !!(val & BIT(APU_GPIO_BIT_DIR));
+}
+
+static int gpio_apu_dir_in(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+   struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val &= ~BIT(APU_GPIO_BIT_DIR);
+   iowrite32(val, apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return 0;
+}
+
+static int gpio_apu_dir_out(struct gpio_chip *chip, unsigned int offset,
+   int value)
+{
+   u32 val;
+   struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio

[PATCH v5 1/2] gpio: Add driver for PC Engines APU boards

2018-11-27 Thread Florian Eckert

Add a new device driver "gpio-apu" which will handle the GPIOs on APU2
and APU3 devices from PC Engines.

APU2 (https://pcengines.ch/schema/apu2c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line

APU3 (https://pcengines.ch/schema/apu3c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line
- G33 is "simswap" connected to SIM switch IC to swap the SIM between
  mPCIe2 and mPCIe3 slot

Signed-off-by: Florian Eckert 
---
 drivers/gpio/Kconfig|   7 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/gpio-apu.c | 288 
 3 files changed, 296 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 833a1b51c948..e89937f6051e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -117,6 +117,13 @@ config GPIO_AMDPT
  driver for GPIO functionality on Promontory IOHub
  Require ACPI ASL code to enumerate as a platform device.
 
+config GPIO_APU
+   tristate "PC Engines APU2/APU3 GPIO support"
+   depends on X86
+   help
+ Say Y here to support GPIO functionality on APU2/APU3 boards
+ from PC Engines.
+
 config GPIO_ASPEED
tristate "Aspeed GPIO support"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 671c4477c951..9c27523fb189 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
 obj-$(CONFIG_GPIO_ALTERA_A10SR)+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)   += gpio-amdpt.o
+obj-$(CONFIG_GPIO_APU) += gpio-apu.o
 obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
 obj-$(CONFIG_GPIO_ATH79)   += gpio-ath79.o
 obj-$(CONFIG_GPIO_ASPEED)  += gpio-aspeed.o
diff --git a/drivers/gpio/gpio-apu.c b/drivers/gpio/gpio-apu.c
new file mode 100644
index ..609972d11847
--- /dev/null
+++ b/drivers/gpio/gpio-apu.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0
+/* PC Engines APU2/APU3 GPIO device driver
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)
+#define APU_GPIO_BIT_RD16
+#define APU_GPIO_BIT_WR22
+#define APU_GPIO_BIT_DIR   23
+
+struct apu_gpio_pdata {
+   struct gpio_chip chip;
+   unsigned long *offset;  /* base register offset */
+   void __iomem **addr;/* remapped iomem addresses */
+   spinlock_t lock;/* lock register access */
+};
+
+static struct platform_device *apu_gpio_pdev;
+
+/* APU2 */
+static unsigned long apu2_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+};
+static const char * const apu2_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+};
+
+/* APU3 */
+static unsigned long apu3_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 90 * sizeof(u32),
+};
+static const char * const apu3_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+   "simswap",
+};
+
+static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+   struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+   spin_lock(_gpio->lock);
+
+   val = ~ioread32(apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return !!(val & BIT(APU_GPIO_BIT_DIR));
+}
+
+static int gpio_apu_dir_in(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+   struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val &= ~BIT(APU_GPIO_BIT_DIR);
+   iowrite32(val, apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return 0;
+}
+
+static int gpio_apu_dir_out(struct gpio_chip *chip, unsigned int offset,
+   int value)
+{
+   u32 val;
+   struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio

[PATCH v5 2/2] platform: Add reset button device for PC Engines APU boards

2018-11-27 Thread Florian Eckert

Add a platform/x86 device "gpio-keys-polled" for the frontpanel reset button.
This device uses the gpio-apu driver for APU borads from PC Engines.

Signed-off-by: Florian Eckert 
---
 drivers/platform/x86/Kconfig  |  11 +++
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/pcengines-apu-platform.c | 114 ++
 3 files changed, 126 insertions(+)
 create mode 100644 drivers/platform/x86/pcengines-apu-platform.c

diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 54f6a40c75c6..5cd27c2174cb 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1288,6 +1288,17 @@ config INTEL_ATOMISP2_PM
  To compile this driver as a module, choose M here: the module
  will be called intel_atomisp2_pm.
 
+config PCENGINES_APU_PLATFORM
+   bool "PCEngines APU System Support"
+   depends on X86_64 && DMI && GPIOLIB
+   help
+ This option enables system support for the PCEngines APU platform.
+ At present this just adds the GPIO reset button platform device on
+ APU2/APU3 boards.
+
+ Note: You must still enable the drivers for GPIO and LED support
+ (GPIO_APU & LEDS_APU) to actually use the LEDs and the GPIOs.
+
 endif # X86_PLATFORM_DEVICES
 
 config PMC_ATOM
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 39ae94135406..f899cc4c6b48 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -96,3 +96,4 @@ obj-$(CONFIG_INTEL_TURBO_MAX_3) += intel_turbo_max_3.o
 obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN)+= intel_chtdc_ti_pwrbtn.o
 obj-$(CONFIG_I2C_MULTI_INSTANTIATE)+= i2c-multi-instantiate.o
 obj-$(CONFIG_INTEL_ATOMISP2_PM)+= intel_atomisp2_pm.o
+obj-$(CONFIG_PCENGINES_APU_PLATFORM)   += pcengines-apu-platform.o
diff --git a/drivers/platform/x86/pcengines-apu-platform.c 
b/drivers/platform/x86/pcengines-apu-platform.c
new file mode 100644
index ..3bfbaa93cb11
--- /dev/null
+++ b/drivers/platform/x86/pcengines-apu-platform.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * System Specific setup for PC-Engines APU2/APU3 devices
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct dmi_system_id apu2_gpio_dmi_table[] __initconst = {
+   /* PC Engines APU2 with "Legacy" bios < 4.0.8 */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "APU2")
+   }
+   },
+   /* PC Engines APU2 with "Legacy" bios >= 4.0.8 */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "apu2")
+   }
+   },
+   /* PC Engines APU2 with "Mainline" bios */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
+   }
+   },
+   {}
+};
+MODULE_DEVICE_TABLE(dmi, apu2_gpio_dmi_table);
+
+static const struct dmi_system_id apu3_gpio_dmi_table[] __initconst = {
+   /* PC Engines APU3 with "Legacy" bios < 4.0.8 */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "APU3")
+   }
+   },
+   /* PC Engines APU3 with "Legacy" bios >= 4.0.8 */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "apu3")
+   }
+   },
+   /* PC Engines APU3 with "Mainline" bios */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu3")
+   }
+   },
+   {}
+};
+MODULE_DEVICE_TABLE(dmi, apu3_gpio_dmi_table);
+
+
+static struct gpio_keys_button apu_gpio_buttons[] = {
+   {
+   .code   = KEY_RESTART,
+   .gpio   = 20,
+   .active_low = 1,
+   .desc   = "Reset button",
+   .type   = EV_KEY,
+   .debounce_interval  = 60,
+   }
+};
+
+static struct gpio

[PATCH v5 2/2] platform: Add reset button device for PC Engines APU boards

2018-11-27 Thread Florian Eckert

Add a platform/x86 device "gpio-keys-polled" for the frontpanel reset button.
This device uses the gpio-apu driver for APU borads from PC Engines.

Signed-off-by: Florian Eckert 
---
 drivers/platform/x86/Kconfig  |  11 +++
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/pcengines-apu-platform.c | 114 ++
 3 files changed, 126 insertions(+)
 create mode 100644 drivers/platform/x86/pcengines-apu-platform.c

diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 54f6a40c75c6..5cd27c2174cb 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1288,6 +1288,17 @@ config INTEL_ATOMISP2_PM
  To compile this driver as a module, choose M here: the module
  will be called intel_atomisp2_pm.
 
+config PCENGINES_APU_PLATFORM
+   bool "PCEngines APU System Support"
+   depends on X86_64 && DMI && GPIOLIB
+   help
+ This option enables system support for the PCEngines APU platform.
+ At present this just adds the GPIO reset button platform device on
+ APU2/APU3 boards.
+
+ Note: You must still enable the drivers for GPIO and LED support
+ (GPIO_APU & LEDS_APU) to actually use the LEDs and the GPIOs.
+
 endif # X86_PLATFORM_DEVICES
 
 config PMC_ATOM
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 39ae94135406..f899cc4c6b48 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -96,3 +96,4 @@ obj-$(CONFIG_INTEL_TURBO_MAX_3) += intel_turbo_max_3.o
 obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN)+= intel_chtdc_ti_pwrbtn.o
 obj-$(CONFIG_I2C_MULTI_INSTANTIATE)+= i2c-multi-instantiate.o
 obj-$(CONFIG_INTEL_ATOMISP2_PM)+= intel_atomisp2_pm.o
+obj-$(CONFIG_PCENGINES_APU_PLATFORM)   += pcengines-apu-platform.o
diff --git a/drivers/platform/x86/pcengines-apu-platform.c 
b/drivers/platform/x86/pcengines-apu-platform.c
new file mode 100644
index ..3bfbaa93cb11
--- /dev/null
+++ b/drivers/platform/x86/pcengines-apu-platform.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * System Specific setup for PC-Engines APU2/APU3 devices
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct dmi_system_id apu2_gpio_dmi_table[] __initconst = {
+   /* PC Engines APU2 with "Legacy" bios < 4.0.8 */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "APU2")
+   }
+   },
+   /* PC Engines APU2 with "Legacy" bios >= 4.0.8 */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "apu2")
+   }
+   },
+   /* PC Engines APU2 with "Mainline" bios */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
+   }
+   },
+   {}
+};
+MODULE_DEVICE_TABLE(dmi, apu2_gpio_dmi_table);
+
+static const struct dmi_system_id apu3_gpio_dmi_table[] __initconst = {
+   /* PC Engines APU3 with "Legacy" bios < 4.0.8 */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "APU3")
+   }
+   },
+   /* PC Engines APU3 with "Legacy" bios >= 4.0.8 */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "apu3")
+   }
+   },
+   /* PC Engines APU3 with "Mainline" bios */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu3")
+   }
+   },
+   {}
+};
+MODULE_DEVICE_TABLE(dmi, apu3_gpio_dmi_table);
+
+
+static struct gpio_keys_button apu_gpio_buttons[] = {
+   {
+   .code   = KEY_RESTART,
+   .gpio   = 20,
+   .active_low = 1,
+   .desc   = "Reset button",
+   .type   = EV_KEY,
+   .debounce_interval  = 60,
+   }
+};
+
+static struct gpio

[PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

2018-11-27 Thread Florian Eckert

Changes v2:
- Update SPDX short identifier
- Remove gpio-keys-polled device moved to arch/x86/platform
- Fix styling
- Use spinnlock only there where it is useful
- Removed useless output on driver load
- Do bit manipulation later not on IO
- Add additional GPIOs handling mpci2_reset and mpcie3_reset.
- Add name to GPIOs exported via sysfs

Changes v3:
- Add a new platform device for the frontpanel push button.
- Get global variables from the heap
- Fix errors/warnings generated by ./scripts/checkpatch.pl

Changes v4:
gpio-apu.c
- Move bit shifting out of spinnlock
- Change declaration of int to unsigned int
- Remove redundant blank line
- Use dmi table callback
- Remove noise
pcengines-apu-platform.c
- Move platform device to drivers/platform/x86
- Remove needless include
- Add dmi information so that this device is only present on APU2
  APU3 boards from PC Engines

Changes v5:
gpio-apu.c
- Remove GPIO_GENERIC select from Kconfig
- Make gpio_chip real member of apu_gpio_pdata
- Use BIT macro for get_data and get_dir functions
- Pass platform data to devm_gpiochip_add_data to get data
  per-instance state container
- Remove DEVNAME define
- Remove platfrom_device member from apu_gpio_pdata this
- Clean up init function
- Remove MODULE_ALIAS

Until now it was not possible to get more information to detect the
MMIO_BASE address from the ACPI subsystem.

Florian Eckert (2):
  gpio: Add driver for PC Engines APU boards
  platform: Add reset button device for PC Engines APU boards

 drivers/gpio/Kconfig  |   7 +
 drivers/gpio/Makefile |   1 +
 drivers/gpio/gpio-apu.c   | 288 ++
 drivers/platform/x86/Kconfig  |  11 +
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/pcengines-apu-platform.c | 114 ++
 6 files changed, 422 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c
 create mode 100644 drivers/platform/x86/pcengines-apu-platform.c

-- 
2.11.0

[PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

2018-11-27 Thread Florian Eckert

Changes v2:
- Update SPDX short identifier
- Remove gpio-keys-polled device moved to arch/x86/platform
- Fix styling
- Use spinnlock only there where it is useful
- Removed useless output on driver load
- Do bit manipulation later not on IO
- Add additional GPIOs handling mpci2_reset and mpcie3_reset.
- Add name to GPIOs exported via sysfs

Changes v3:
- Add a new platform device for the frontpanel push button.
- Get global variables from the heap
- Fix errors/warnings generated by ./scripts/checkpatch.pl

Changes v4:
gpio-apu.c
- Move bit shifting out of spinnlock
- Change declaration of int to unsigned int
- Remove redundant blank line
- Use dmi table callback
- Remove noise
pcengines-apu-platform.c
- Move platform device to drivers/platform/x86
- Remove needless include
- Add dmi information so that this device is only present on APU2
  APU3 boards from PC Engines

Changes v5:
gpio-apu.c
- Remove GPIO_GENERIC select from Kconfig
- Make gpio_chip real member of apu_gpio_pdata
- Use BIT macro for get_data and get_dir functions
- Pass platform data to devm_gpiochip_add_data to get data
  per-instance state container
- Remove DEVNAME define
- Remove platfrom_device member from apu_gpio_pdata this
- Clean up init function
- Remove MODULE_ALIAS

Until now it was not possible to get more information to detect the
MMIO_BASE address from the ACPI subsystem.

Florian Eckert (2):
  gpio: Add driver for PC Engines APU boards
  platform: Add reset button device for PC Engines APU boards

 drivers/gpio/Kconfig  |   7 +
 drivers/gpio/Makefile |   1 +
 drivers/gpio/gpio-apu.c   | 288 ++
 drivers/platform/x86/Kconfig  |  11 +
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/pcengines-apu-platform.c | 114 ++
 6 files changed, 422 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c
 create mode 100644 drivers/platform/x86/pcengines-apu-platform.c

-- 
2.11.0

Re: [PATCH v4 1/2] gpio: Add driver for PC Engines APU boards

2018-11-19 Thread Florian Eckert


Hello Linus


Signed-off-by: Florian Eckert 


This is looking better and better! Thanks to everyone helping out
and thanks for your perseverance Florian!



I have to thanks for reviewing my driver.
This is the way opensource works.

Thanks for the feedback i will update the driver with your suggestions.

  - Florian

Re: [PATCH v4 1/2] gpio: Add driver for PC Engines APU boards

2018-11-19 Thread Florian Eckert


Hello Linus


Signed-off-by: Florian Eckert 


This is looking better and better! Thanks to everyone helping out
and thanks for your perseverance Florian!



I have to thanks for reviewing my driver.
This is the way opensource works.

Thanks for the feedback i will update the driver with your suggestions.

  - Florian

[PATCH v4 2/2] platform: Add reset button device for PC Engines APU boards

2018-11-15 Thread Florian Eckert

Add a platform/x86 device "gpio-keys-polled" for the frontpanel reset button.
This device uses the gpio-apu driver for APU borads from PC Engines.

Signed-off-by: Florian Eckert 
---
 drivers/platform/x86/Kconfig  |  11 +++
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/pcengines-apu-platform.c | 114 ++
 3 files changed, 126 insertions(+)
 create mode 100644 drivers/platform/x86/pcengines-apu-platform.c

diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 54f6a40c75c6..5cd27c2174cb 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1288,6 +1288,17 @@ config INTEL_ATOMISP2_PM
  To compile this driver as a module, choose M here: the module
  will be called intel_atomisp2_pm.
 
+config PCENGINES_APU_PLATFORM
+   bool "PCEngines APU System Support"
+   depends on X86_64 && DMI && GPIOLIB
+   help
+ This option enables system support for the PCEngines APU platform.
+ At present this just adds the GPIO reset button platform device on
+ APU2/APU3 boards.
+
+ Note: You must still enable the drivers for GPIO and LED support
+ (GPIO_APU & LEDS_APU) to actually use the LEDs and the GPIOs.
+
 endif # X86_PLATFORM_DEVICES
 
 config PMC_ATOM
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 39ae94135406..f899cc4c6b48 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -96,3 +96,4 @@ obj-$(CONFIG_INTEL_TURBO_MAX_3) += intel_turbo_max_3.o
 obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN)+= intel_chtdc_ti_pwrbtn.o
 obj-$(CONFIG_I2C_MULTI_INSTANTIATE)+= i2c-multi-instantiate.o
 obj-$(CONFIG_INTEL_ATOMISP2_PM)+= intel_atomisp2_pm.o
+obj-$(CONFIG_PCENGINES_APU_PLATFORM)   += pcengines-apu-platform.o
diff --git a/drivers/platform/x86/pcengines-apu-platform.c 
b/drivers/platform/x86/pcengines-apu-platform.c
new file mode 100644
index ..3bfbaa93cb11
--- /dev/null
+++ b/drivers/platform/x86/pcengines-apu-platform.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * System Specific setup for PC-Engines APU2/APU3 devices
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct dmi_system_id apu2_gpio_dmi_table[] __initconst = {
+   /* PC Engines APU2 with "Legacy" bios < 4.0.8 */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "APU2")
+   }
+   },
+   /* PC Engines APU2 with "Legacy" bios >= 4.0.8 */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "apu2")
+   }
+   },
+   /* PC Engines APU2 with "Mainline" bios */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
+   }
+   },
+   {}
+};
+MODULE_DEVICE_TABLE(dmi, apu2_gpio_dmi_table);
+
+static const struct dmi_system_id apu3_gpio_dmi_table[] __initconst = {
+   /* PC Engines APU3 with "Legacy" bios < 4.0.8 */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "APU3")
+   }
+   },
+   /* PC Engines APU3 with "Legacy" bios >= 4.0.8 */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "apu3")
+   }
+   },
+   /* PC Engines APU3 with "Mainline" bios */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu3")
+   }
+   },
+   {}
+};
+MODULE_DEVICE_TABLE(dmi, apu3_gpio_dmi_table);
+
+
+static struct gpio_keys_button apu_gpio_buttons[] = {
+   {
+   .code   = KEY_RESTART,
+   .gpio   = 20,
+   .active_low = 1,
+   .desc   = "Reset button",
+   .type   = EV_KEY,
+   .debounce_interval  = 60,
+   }
+};
+
+static struct gpio

[PATCH v4 2/2] platform: Add reset button device for PC Engines APU boards

2018-11-15 Thread Florian Eckert

Add a platform/x86 device "gpio-keys-polled" for the frontpanel reset button.
This device uses the gpio-apu driver for APU borads from PC Engines.

Signed-off-by: Florian Eckert 
---
 drivers/platform/x86/Kconfig  |  11 +++
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/pcengines-apu-platform.c | 114 ++
 3 files changed, 126 insertions(+)
 create mode 100644 drivers/platform/x86/pcengines-apu-platform.c

diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 54f6a40c75c6..5cd27c2174cb 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1288,6 +1288,17 @@ config INTEL_ATOMISP2_PM
  To compile this driver as a module, choose M here: the module
  will be called intel_atomisp2_pm.
 
+config PCENGINES_APU_PLATFORM
+   bool "PCEngines APU System Support"
+   depends on X86_64 && DMI && GPIOLIB
+   help
+ This option enables system support for the PCEngines APU platform.
+ At present this just adds the GPIO reset button platform device on
+ APU2/APU3 boards.
+
+ Note: You must still enable the drivers for GPIO and LED support
+ (GPIO_APU & LEDS_APU) to actually use the LEDs and the GPIOs.
+
 endif # X86_PLATFORM_DEVICES
 
 config PMC_ATOM
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 39ae94135406..f899cc4c6b48 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -96,3 +96,4 @@ obj-$(CONFIG_INTEL_TURBO_MAX_3) += intel_turbo_max_3.o
 obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN)+= intel_chtdc_ti_pwrbtn.o
 obj-$(CONFIG_I2C_MULTI_INSTANTIATE)+= i2c-multi-instantiate.o
 obj-$(CONFIG_INTEL_ATOMISP2_PM)+= intel_atomisp2_pm.o
+obj-$(CONFIG_PCENGINES_APU_PLATFORM)   += pcengines-apu-platform.o
diff --git a/drivers/platform/x86/pcengines-apu-platform.c 
b/drivers/platform/x86/pcengines-apu-platform.c
new file mode 100644
index ..3bfbaa93cb11
--- /dev/null
+++ b/drivers/platform/x86/pcengines-apu-platform.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * System Specific setup for PC-Engines APU2/APU3 devices
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct dmi_system_id apu2_gpio_dmi_table[] __initconst = {
+   /* PC Engines APU2 with "Legacy" bios < 4.0.8 */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "APU2")
+   }
+   },
+   /* PC Engines APU2 with "Legacy" bios >= 4.0.8 */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "apu2")
+   }
+   },
+   /* PC Engines APU2 with "Mainline" bios */
+   {
+   .ident = "apu2",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
+   }
+   },
+   {}
+};
+MODULE_DEVICE_TABLE(dmi, apu2_gpio_dmi_table);
+
+static const struct dmi_system_id apu3_gpio_dmi_table[] __initconst = {
+   /* PC Engines APU3 with "Legacy" bios < 4.0.8 */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "APU3")
+   }
+   },
+   /* PC Engines APU3 with "Legacy" bios >= 4.0.8 */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "apu3")
+   }
+   },
+   /* PC Engines APU3 with "Mainline" bios */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu3")
+   }
+   },
+   {}
+};
+MODULE_DEVICE_TABLE(dmi, apu3_gpio_dmi_table);
+
+
+static struct gpio_keys_button apu_gpio_buttons[] = {
+   {
+   .code   = KEY_RESTART,
+   .gpio   = 20,
+   .active_low = 1,
+   .desc   = "Reset button",
+   .type   = EV_KEY,
+   .debounce_interval  = 60,
+   }
+};
+
+static struct gpio

[PATCH v4 0/2] Add device driver for APU2/APU3 GPIOs

2018-11-15 Thread Florian Eckert

Changes v2:
- Update SPDX short identifier
- Remove gpio-keys-polled device moved to arch/x86/platform
- Fix styling
- Use spinnlock only there where it is useful
- Removed useless output on driver load
- Do bit manipulation later not on IO
- Add additional GPIOs handling mpci2_reset and mpcie3_reset.
- Add name to GPIOs exported via sysfs

Changes v3:
- Add a new platform device for the frontpanel push button.
- Get global variables from the heap
- Fix errors/warnings generated by ./scripts/checkpatch.pl

Changes v4:
gpio-apu.c
- Move bit shifting out of spinnlock
- Change declaration of int to unsigned int
- Remove redundant blank line
- Use dmi table callback
- Remove noise
pcengines-apu-platform.c
- Move platform device to drivers/platform/x86
- Remove needless include
- Add dmi information so that this device is only present on APU2
  APU3 boards from PC Engines

Until now it was not possible to get more information to detect the
MMIO_BASE address from the ACPI subsystem.

Florian Eckert (2):
  gpio: Add driver for PC Engines APU boards
  platform: Add reset button device for PC Engines APU boards

 drivers/gpio/Kconfig  |   8 +
 drivers/gpio/Makefile |   1 +
 drivers/gpio/gpio-apu.c   | 299 ++
 drivers/platform/x86/Kconfig  |  11 +
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/pcengines-apu-platform.c | 114 ++
 6 files changed, 434 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c
 create mode 100644 drivers/platform/x86/pcengines-apu-platform.c

-- 
2.11.0

[PATCH v4 0/2] Add device driver for APU2/APU3 GPIOs

2018-11-15 Thread Florian Eckert

Changes v2:
- Update SPDX short identifier
- Remove gpio-keys-polled device moved to arch/x86/platform
- Fix styling
- Use spinnlock only there where it is useful
- Removed useless output on driver load
- Do bit manipulation later not on IO
- Add additional GPIOs handling mpci2_reset and mpcie3_reset.
- Add name to GPIOs exported via sysfs

Changes v3:
- Add a new platform device for the frontpanel push button.
- Get global variables from the heap
- Fix errors/warnings generated by ./scripts/checkpatch.pl

Changes v4:
gpio-apu.c
- Move bit shifting out of spinnlock
- Change declaration of int to unsigned int
- Remove redundant blank line
- Use dmi table callback
- Remove noise
pcengines-apu-platform.c
- Move platform device to drivers/platform/x86
- Remove needless include
- Add dmi information so that this device is only present on APU2
  APU3 boards from PC Engines

Until now it was not possible to get more information to detect the
MMIO_BASE address from the ACPI subsystem.

Florian Eckert (2):
  gpio: Add driver for PC Engines APU boards
  platform: Add reset button device for PC Engines APU boards

 drivers/gpio/Kconfig  |   8 +
 drivers/gpio/Makefile |   1 +
 drivers/gpio/gpio-apu.c   | 299 ++
 drivers/platform/x86/Kconfig  |  11 +
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/pcengines-apu-platform.c | 114 ++
 6 files changed, 434 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c
 create mode 100644 drivers/platform/x86/pcengines-apu-platform.c

-- 
2.11.0

[PATCH v4 1/2] gpio: Add driver for PC Engines APU boards

2018-11-15 Thread Florian Eckert

Add a new device driver "gpio-apu" which will handle the GPIOs on APU2
and APU3 devices from PC Engines.

APU2 (https://pcengines.ch/schema/apu2c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line

APU3 (https://pcengines.ch/schema/apu3c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line
- G33 is "simswap" connected to SIM switch IC to swap the SIM between
  mPCIe2 and mPCIe3 slot

Signed-off-by: Florian Eckert 
---
 drivers/gpio/Kconfig|   8 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/gpio-apu.c | 299 
 3 files changed, 308 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 833a1b51c948..f9e603d5670c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -117,6 +117,14 @@ config GPIO_AMDPT
  driver for GPIO functionality on Promontory IOHub
  Require ACPI ASL code to enumerate as a platform device.
 
+config GPIO_APU
+   tristate "PC Engines APU2/APU3 GPIO support"
+   depends on X86
+   select GPIO_GENERIC
+   help
+ Say Y here to support GPIO functionality on APU2/APU3 boards
+ from PC Engines.
+
 config GPIO_ASPEED
tristate "Aspeed GPIO support"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 671c4477c951..9c27523fb189 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
 obj-$(CONFIG_GPIO_ALTERA_A10SR)+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)   += gpio-amdpt.o
+obj-$(CONFIG_GPIO_APU) += gpio-apu.o
 obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
 obj-$(CONFIG_GPIO_ATH79)   += gpio-ath79.o
 obj-$(CONFIG_GPIO_ASPEED)  += gpio-aspeed.o
diff --git a/drivers/gpio/gpio-apu.c b/drivers/gpio/gpio-apu.c
new file mode 100644
index ..cd7788edebab
--- /dev/null
+++ b/drivers/gpio/gpio-apu.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+/* PC Engines APU2/APU3 GPIO device driver
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEVNAME"gpio-apu"
+
+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)
+#define APU_GPIO_BIT_RD16
+#define APU_GPIO_BIT_WR22
+#define APU_GPIO_BIT_DIR   23
+
+struct apu_gpio_pdata {
+   struct platform_device *pdev;
+   struct gpio_chip *chip;
+   unsigned long *offset;  /* base register offset */
+   void __iomem **addr;/* remapped iomem addresses */
+   spinlock_t lock;/* lock register access */
+};
+
+static struct apu_gpio_pdata *apu_gpio;
+
+/* APU2 */
+static unsigned long apu2_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+};
+static const char * const apu2_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+};
+
+/* APU3 */
+static unsigned long apu3_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 90 * sizeof(u32),
+};
+static const char * const apu3_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+   "simswap",
+};
+
+static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ~ioread32(apu_gpio->addr[offset]);
+   val = (val >> APU_GPIO_BIT_DIR) & 1;
+
+   spin_unlock(_gpio->lock);
+
+   return val;
+}
+
+static int gpio_apu_dir_in(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val &= ~BIT(APU_GPIO_BIT_DIR);
+   iowrite32(val, apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return 0;
+}
+
+static int gpio_apu_dir_out(struct gpio_chip *chip, unsigned int offset,
+   int value)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val |= BIT(APU_GPIO_BIT_DIR);
+

[PATCH v4 1/2] gpio: Add driver for PC Engines APU boards

2018-11-15 Thread Florian Eckert

Add a new device driver "gpio-apu" which will handle the GPIOs on APU2
and APU3 devices from PC Engines.

APU2 (https://pcengines.ch/schema/apu2c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line

APU3 (https://pcengines.ch/schema/apu3c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line
- G33 is "simswap" connected to SIM switch IC to swap the SIM between
  mPCIe2 and mPCIe3 slot

Signed-off-by: Florian Eckert 
---
 drivers/gpio/Kconfig|   8 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/gpio-apu.c | 299 
 3 files changed, 308 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 833a1b51c948..f9e603d5670c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -117,6 +117,14 @@ config GPIO_AMDPT
  driver for GPIO functionality on Promontory IOHub
  Require ACPI ASL code to enumerate as a platform device.
 
+config GPIO_APU
+   tristate "PC Engines APU2/APU3 GPIO support"
+   depends on X86
+   select GPIO_GENERIC
+   help
+ Say Y here to support GPIO functionality on APU2/APU3 boards
+ from PC Engines.
+
 config GPIO_ASPEED
tristate "Aspeed GPIO support"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 671c4477c951..9c27523fb189 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
 obj-$(CONFIG_GPIO_ALTERA_A10SR)+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)   += gpio-amdpt.o
+obj-$(CONFIG_GPIO_APU) += gpio-apu.o
 obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
 obj-$(CONFIG_GPIO_ATH79)   += gpio-ath79.o
 obj-$(CONFIG_GPIO_ASPEED)  += gpio-aspeed.o
diff --git a/drivers/gpio/gpio-apu.c b/drivers/gpio/gpio-apu.c
new file mode 100644
index ..cd7788edebab
--- /dev/null
+++ b/drivers/gpio/gpio-apu.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+/* PC Engines APU2/APU3 GPIO device driver
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEVNAME"gpio-apu"
+
+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)
+#define APU_GPIO_BIT_RD16
+#define APU_GPIO_BIT_WR22
+#define APU_GPIO_BIT_DIR   23
+
+struct apu_gpio_pdata {
+   struct platform_device *pdev;
+   struct gpio_chip *chip;
+   unsigned long *offset;  /* base register offset */
+   void __iomem **addr;/* remapped iomem addresses */
+   spinlock_t lock;/* lock register access */
+};
+
+static struct apu_gpio_pdata *apu_gpio;
+
+/* APU2 */
+static unsigned long apu2_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+};
+static const char * const apu2_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+};
+
+/* APU3 */
+static unsigned long apu3_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 90 * sizeof(u32),
+};
+static const char * const apu3_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+   "simswap",
+};
+
+static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ~ioread32(apu_gpio->addr[offset]);
+   val = (val >> APU_GPIO_BIT_DIR) & 1;
+
+   spin_unlock(_gpio->lock);
+
+   return val;
+}
+
+static int gpio_apu_dir_in(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val &= ~BIT(APU_GPIO_BIT_DIR);
+   iowrite32(val, apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return 0;
+}
+
+static int gpio_apu_dir_out(struct gpio_chip *chip, unsigned int offset,
+   int value)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val |= BIT(APU_GPIO_BIT_DIR);
+

[PATCH v3 0/2] Add device driver for APU2/APU3 GPIOs

2018-11-13 Thread Florian Eckert

Changes v2:
- Update SPDX short identifier
- Remove gpio-keys-polled device moved to arch/x86/platform
- Fix styling
- Use spinnlock only there where it is useful
- Removed useless output on driver load
- Do bit manipulation later not on IO
- Add additional GPIOs handling mpci2_reset and mpcie3_reset.
- Add name to GPIOs exported via sysfs

Changes v3:
- Add a new platform device for the frontpanel push button.
- Get global variables from the heap
- Fix errors/warnings generated by ./scripts/checkpatch.pl

Until now it was not possible to get more information to detect the
MMIO_BASE address from the ACPI subsystem.


Florian Eckert (2):
  gpio: Add driver for PC Engines APU2/APU3 GPIOs
  kernel: Add reset button platform device for APU2/APU3

 arch/x86/Kconfig   |  14 ++
 arch/x86/platform/Makefile |   1 +
 arch/x86/platform/amd/Makefile |   1 +
 arch/x86/platform/amd/apu.c|  72 ++
 drivers/gpio/Kconfig   |   8 ++
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-apu.c| 316 +
 7 files changed, 413 insertions(+)
 create mode 100644 arch/x86/platform/amd/Makefile
 create mode 100644 arch/x86/platform/amd/apu.c
 create mode 100644 drivers/gpio/gpio-apu.c

-- 
2.11.0

[PATCH v3 0/2] Add device driver for APU2/APU3 GPIOs

2018-11-13 Thread Florian Eckert

Changes v2:
- Update SPDX short identifier
- Remove gpio-keys-polled device moved to arch/x86/platform
- Fix styling
- Use spinnlock only there where it is useful
- Removed useless output on driver load
- Do bit manipulation later not on IO
- Add additional GPIOs handling mpci2_reset and mpcie3_reset.
- Add name to GPIOs exported via sysfs

Changes v3:
- Add a new platform device for the frontpanel push button.
- Get global variables from the heap
- Fix errors/warnings generated by ./scripts/checkpatch.pl

Until now it was not possible to get more information to detect the
MMIO_BASE address from the ACPI subsystem.


Florian Eckert (2):
  gpio: Add driver for PC Engines APU2/APU3 GPIOs
  kernel: Add reset button platform device for APU2/APU3

 arch/x86/Kconfig   |  14 ++
 arch/x86/platform/Makefile |   1 +
 arch/x86/platform/amd/Makefile |   1 +
 arch/x86/platform/amd/apu.c|  72 ++
 drivers/gpio/Kconfig   |   8 ++
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-apu.c| 316 +
 7 files changed, 413 insertions(+)
 create mode 100644 arch/x86/platform/amd/Makefile
 create mode 100644 arch/x86/platform/amd/apu.c
 create mode 100644 drivers/gpio/gpio-apu.c

-- 
2.11.0

[PATCH v3 1/2] gpio: Add driver for PC Engines APU2/APU3 GPIOs

2018-11-13 Thread Florian Eckert

Add a new device driver "gpio-apu" which will handle the GPIOs onAPU2
and APU3 devices from PC Engines.

APU2 (https://pcengines.ch/schema/apu2c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line

APU3 (https://pcengines.ch/schema/apu3c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line
- G33 is "simswap" connected to SIM switch IC to swap the SIM between
  mPCIe2 and mPCIe3 slot

Signed-off-by: Florian Eckert 
---
 drivers/gpio/Kconfig|   8 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/gpio-apu.c | 312 
 3 files changed, 321 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 833a1b51c948..f9e603d5670c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -117,6 +117,14 @@ config GPIO_AMDPT
  driver for GPIO functionality on Promontory IOHub
  Require ACPI ASL code to enumerate as a platform device.
 
+config GPIO_APU
+   tristate "PC Engines APU2/APU3 GPIO support"
+   depends on X86
+   select GPIO_GENERIC
+   help
+ Say Y here to support GPIO functionality on APU2/APU3 boards
+ from PC Engines.
+
 config GPIO_ASPEED
tristate "Aspeed GPIO support"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 671c4477c951..9c27523fb189 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
 obj-$(CONFIG_GPIO_ALTERA_A10SR)+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)   += gpio-amdpt.o
+obj-$(CONFIG_GPIO_APU) += gpio-apu.o
 obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
 obj-$(CONFIG_GPIO_ATH79)   += gpio-ath79.o
 obj-$(CONFIG_GPIO_ASPEED)  += gpio-aspeed.o
diff --git a/drivers/gpio/gpio-apu.c b/drivers/gpio/gpio-apu.c
new file mode 100644
index ..df166c0d8258
--- /dev/null
+++ b/drivers/gpio/gpio-apu.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0
+/* PC Engines APU2/APU3 GPIO device driver
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEVNAME"gpio-apu"
+
+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)
+#define APU_GPIO_BIT_RD16
+#define APU_GPIO_BIT_WR22
+#define APU_GPIO_BIT_DIR   23
+
+struct apu_gpio_pdata {
+   struct platform_device *pdev;
+   struct gpio_chip *chip;
+   unsigned long *offset;  /* base register offset */
+   void __iomem **addr;/* remapped iomem addresses */
+   spinlock_t lock;/* lock register access */
+};
+
+static struct apu_gpio_pdata *apu_gpio;
+
+/* APU2 */
+static unsigned long apu2_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+};
+static const char * const apu2_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+};
+
+/* APU3 */
+static unsigned long apu3_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 90 * sizeof(u32),
+};
+static const char * const apu3_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+   "simswap",
+};
+
+static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ~ioread32(apu_gpio->addr[offset]);
+   val = (val >> APU_GPIO_BIT_DIR) & 1;
+
+   spin_unlock(_gpio->lock);
+
+   return val;
+}
+
+static int gpio_apu_dir_in(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val &= ~BIT(APU_GPIO_BIT_DIR);
+   iowrite32(val, apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return 0;
+}
+
+static int gpio_apu_dir_out(struct gpio_chip *chip, unsigned int offset,
+   int value)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val |= BIT(APU_GPIO_BIT_DIR);
+

[PATCH v3 1/2] gpio: Add driver for PC Engines APU2/APU3 GPIOs

2018-11-13 Thread Florian Eckert

Add a new device driver "gpio-apu" which will handle the GPIOs onAPU2
and APU3 devices from PC Engines.

APU2 (https://pcengines.ch/schema/apu2c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line

APU3 (https://pcengines.ch/schema/apu3c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line
- G33 is "simswap" connected to SIM switch IC to swap the SIM between
  mPCIe2 and mPCIe3 slot

Signed-off-by: Florian Eckert 
---
 drivers/gpio/Kconfig|   8 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/gpio-apu.c | 312 
 3 files changed, 321 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 833a1b51c948..f9e603d5670c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -117,6 +117,14 @@ config GPIO_AMDPT
  driver for GPIO functionality on Promontory IOHub
  Require ACPI ASL code to enumerate as a platform device.
 
+config GPIO_APU
+   tristate "PC Engines APU2/APU3 GPIO support"
+   depends on X86
+   select GPIO_GENERIC
+   help
+ Say Y here to support GPIO functionality on APU2/APU3 boards
+ from PC Engines.
+
 config GPIO_ASPEED
tristate "Aspeed GPIO support"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 671c4477c951..9c27523fb189 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
 obj-$(CONFIG_GPIO_ALTERA_A10SR)+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)   += gpio-amdpt.o
+obj-$(CONFIG_GPIO_APU) += gpio-apu.o
 obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
 obj-$(CONFIG_GPIO_ATH79)   += gpio-ath79.o
 obj-$(CONFIG_GPIO_ASPEED)  += gpio-aspeed.o
diff --git a/drivers/gpio/gpio-apu.c b/drivers/gpio/gpio-apu.c
new file mode 100644
index ..df166c0d8258
--- /dev/null
+++ b/drivers/gpio/gpio-apu.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0
+/* PC Engines APU2/APU3 GPIO device driver
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEVNAME"gpio-apu"
+
+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)
+#define APU_GPIO_BIT_RD16
+#define APU_GPIO_BIT_WR22
+#define APU_GPIO_BIT_DIR   23
+
+struct apu_gpio_pdata {
+   struct platform_device *pdev;
+   struct gpio_chip *chip;
+   unsigned long *offset;  /* base register offset */
+   void __iomem **addr;/* remapped iomem addresses */
+   spinlock_t lock;/* lock register access */
+};
+
+static struct apu_gpio_pdata *apu_gpio;
+
+/* APU2 */
+static unsigned long apu2_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+};
+static const char * const apu2_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+};
+
+/* APU3 */
+static unsigned long apu3_gpio_offset[] = {
+   APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+   APU_FCH_GPIO_BASE + 90 * sizeof(u32),
+};
+static const char * const apu3_gpio_names[] = {
+   "button_reset",
+   "mpcie2_reset",
+   "mpcie3_reset",
+   "simswap",
+};
+
+static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ~ioread32(apu_gpio->addr[offset]);
+   val = (val >> APU_GPIO_BIT_DIR) & 1;
+
+   spin_unlock(_gpio->lock);
+
+   return val;
+}
+
+static int gpio_apu_dir_in(struct gpio_chip *chip, unsigned int offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val &= ~BIT(APU_GPIO_BIT_DIR);
+   iowrite32(val, apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return 0;
+}
+
+static int gpio_apu_dir_out(struct gpio_chip *chip, unsigned int offset,
+   int value)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val |= BIT(APU_GPIO_BIT_DIR);
+

[PATCH v3 2/2] kernel: Add reset button platform device for APU2/APU3

2018-11-13 Thread Florian Eckert

This will add a x86 platform device "gpio-keys-polled" which uses the
new gpio-apu drive for APU2 and APU3 boards from PC Engines.

Signed-off-by: Florian Eckert 
---
 arch/x86/Kconfig   | 14 
 arch/x86/platform/Makefile |  1 +
 arch/x86/platform/amd/Makefile |  1 +
 arch/x86/platform/amd/apu.c| 72 ++
 4 files changed, 88 insertions(+)
 create mode 100644 arch/x86/platform/amd/Makefile
 create mode 100644 arch/x86/platform/amd/apu.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 9d734f3c8234..97c53286fdb6 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2820,6 +2820,20 @@ config TS5500
 
 endif # X86_32
 
+if X86_64
+config APU
+   bool "PCEngines APU System Support"
+   help
+ This option enables system support for the PCEngines APU platform.
+ At present this just sets up the reset button control on
+ APU2/APU3 boards. However, other system specific setup should
+ get added here.
+
+ Note: You must still enable the drivers for GPIO and LED support
+ (GPIO_APU & LEDS_APU) to actually use the LEDs and the GPIOs
+
+endif # X86_64
+
 config AMD_NB
def_bool y
depends on CPU_SUP_AMD && PCI
diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile
index d0e835470d01..a95d18810c29 100644
--- a/arch/x86/platform/Makefile
+++ b/arch/x86/platform/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 # Platform specific code goes here
 obj-y  += atom/
+obj-y  += amd/
 obj-y  += ce4100/
 obj-y  += efi/
 obj-y  += geode/
diff --git a/arch/x86/platform/amd/Makefile b/arch/x86/platform/amd/Makefile
new file mode 100644
index ..bf04c5799d7f
--- /dev/null
+++ b/arch/x86/platform/amd/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_APU)  +=apu.o
diff --git a/arch/x86/platform/amd/apu.c b/arch/x86/platform/amd/apu.c
new file mode 100644
index ..a4b695881177
--- /dev/null
+++ b/arch/x86/platform/amd/apu.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * System Specific setup for PC-Engines APU2/APU3 devices
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static struct gpio_keys_button apu_gpio_buttons[] = {
+   {
+   .code   = KEY_RESTART,
+   .gpio   = 20,
+   .active_low = 1,
+   .desc   = "Reset button",
+   .type   = EV_KEY,
+   .debounce_interval  = 60,
+   }
+};
+
+static struct gpio_keys_platform_data apu_buttons_data = {
+   .buttons= apu_gpio_buttons,
+   .nbuttons   = ARRAY_SIZE(apu_gpio_buttons),
+   .poll_interval  = 20,
+};
+
+static struct platform_device apu_buttons_dev = {
+   .name   = "gpio-keys-polled",
+   .id = 1,
+   .dev = {
+   .platform_data  = _buttons_data,
+   }
+};
+
+static struct platform_device *apu_devs[] __initdata = {
+   _buttons_dev,
+};
+
+static void __init register_apu(void)
+{
+   /* Setup push button control through gpio-apu driver */
+   platform_add_devices(apu_devs, ARRAY_SIZE(apu_devs));
+}
+
+static int __init apu_init(void)
+{
+   if (!dmi_match(DMI_SYS_VENDOR, "PC Engines")) {
+   pr_err("No PC Engines board detected\n");
+   return -ENODEV;
+   }
+
+   if (!(dmi_match(DMI_PRODUCT_NAME, "APU2") ||
+ dmi_match(DMI_PRODUCT_NAME, "apu2") ||
+ dmi_match(DMI_PRODUCT_NAME, "PC Engines apu2") ||
+ dmi_match(DMI_PRODUCT_NAME, "APU3") ||
+ dmi_match(DMI_PRODUCT_NAME, "apu3") ||
+ dmi_match(DMI_PRODUCT_NAME, "PC Engines apu3"))) {
+   pr_err("Unknown PC Engines board: %s\n",
+   dmi_get_system_info(DMI_PRODUCT_NAME));
+   return -ENODEV;
+   }
+
+   register_apu();
+
+   return 0;
+}
+
+device_initcall(apu_init);
-- 
2.11.0

[PATCH v3 2/2] kernel: Add reset button platform device for APU2/APU3

2018-11-13 Thread Florian Eckert

This will add a x86 platform device "gpio-keys-polled" which uses the
new gpio-apu drive for APU2 and APU3 boards from PC Engines.

Signed-off-by: Florian Eckert 
---
 arch/x86/Kconfig   | 14 
 arch/x86/platform/Makefile |  1 +
 arch/x86/platform/amd/Makefile |  1 +
 arch/x86/platform/amd/apu.c| 72 ++
 4 files changed, 88 insertions(+)
 create mode 100644 arch/x86/platform/amd/Makefile
 create mode 100644 arch/x86/platform/amd/apu.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 9d734f3c8234..97c53286fdb6 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2820,6 +2820,20 @@ config TS5500
 
 endif # X86_32
 
+if X86_64
+config APU
+   bool "PCEngines APU System Support"
+   help
+ This option enables system support for the PCEngines APU platform.
+ At present this just sets up the reset button control on
+ APU2/APU3 boards. However, other system specific setup should
+ get added here.
+
+ Note: You must still enable the drivers for GPIO and LED support
+ (GPIO_APU & LEDS_APU) to actually use the LEDs and the GPIOs
+
+endif # X86_64
+
 config AMD_NB
def_bool y
depends on CPU_SUP_AMD && PCI
diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile
index d0e835470d01..a95d18810c29 100644
--- a/arch/x86/platform/Makefile
+++ b/arch/x86/platform/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 # Platform specific code goes here
 obj-y  += atom/
+obj-y  += amd/
 obj-y  += ce4100/
 obj-y  += efi/
 obj-y  += geode/
diff --git a/arch/x86/platform/amd/Makefile b/arch/x86/platform/amd/Makefile
new file mode 100644
index ..bf04c5799d7f
--- /dev/null
+++ b/arch/x86/platform/amd/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_APU)  +=apu.o
diff --git a/arch/x86/platform/amd/apu.c b/arch/x86/platform/amd/apu.c
new file mode 100644
index ..a4b695881177
--- /dev/null
+++ b/arch/x86/platform/amd/apu.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * System Specific setup for PC-Engines APU2/APU3 devices
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static struct gpio_keys_button apu_gpio_buttons[] = {
+   {
+   .code   = KEY_RESTART,
+   .gpio   = 20,
+   .active_low = 1,
+   .desc   = "Reset button",
+   .type   = EV_KEY,
+   .debounce_interval  = 60,
+   }
+};
+
+static struct gpio_keys_platform_data apu_buttons_data = {
+   .buttons= apu_gpio_buttons,
+   .nbuttons   = ARRAY_SIZE(apu_gpio_buttons),
+   .poll_interval  = 20,
+};
+
+static struct platform_device apu_buttons_dev = {
+   .name   = "gpio-keys-polled",
+   .id = 1,
+   .dev = {
+   .platform_data  = _buttons_data,
+   }
+};
+
+static struct platform_device *apu_devs[] __initdata = {
+   _buttons_dev,
+};
+
+static void __init register_apu(void)
+{
+   /* Setup push button control through gpio-apu driver */
+   platform_add_devices(apu_devs, ARRAY_SIZE(apu_devs));
+}
+
+static int __init apu_init(void)
+{
+   if (!dmi_match(DMI_SYS_VENDOR, "PC Engines")) {
+   pr_err("No PC Engines board detected\n");
+   return -ENODEV;
+   }
+
+   if (!(dmi_match(DMI_PRODUCT_NAME, "APU2") ||
+ dmi_match(DMI_PRODUCT_NAME, "apu2") ||
+ dmi_match(DMI_PRODUCT_NAME, "PC Engines apu2") ||
+ dmi_match(DMI_PRODUCT_NAME, "APU3") ||
+ dmi_match(DMI_PRODUCT_NAME, "apu3") ||
+ dmi_match(DMI_PRODUCT_NAME, "PC Engines apu3"))) {
+   pr_err("Unknown PC Engines board: %s\n",
+   dmi_get_system_info(DMI_PRODUCT_NAME));
+   return -ENODEV;
+   }
+
+   register_apu();
+
+   return 0;
+}
+
+device_initcall(apu_init);
-- 
2.11.0

Re: [PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs

2018-08-29 Thread Florian Eckert


On 2018-08-24 12:56, Piotr Król wrote:

On 08/03/2018 09:08 PM, Andy Shevchenko wrote:

Hi Andy,

(...)


+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)


Wow! Can we see ACPI tables for these boards? Care to share (via some
file share service) output of `acpidump -o tables.dat` ?


Please find acpidump [1]. FYI I'm PC Engines firmware maintainer
(firmware is coreboot based), so I can fix required things. I'm pretty
sure that ACPI tables are not in best shape.



Thanks for the dump,

By the way I have seen that the driver
https://github.com/torvalds/linux/blob/master/drivers/gpio/gpio-amdpt.c
is using the acpi to get the mmio address. I think this is the way to go
to get the acpi mmio address in the gpio-apu driver as well.

What is the right "acpi_device_id" for the APU3?
https://github.com/torvalds/linux/blob/master/drivers/gpio/gpio-amdpt.c#L146

Re: [PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs

2018-08-29 Thread Florian Eckert


On 2018-08-24 12:56, Piotr Król wrote:

On 08/03/2018 09:08 PM, Andy Shevchenko wrote:

Hi Andy,

(...)


+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)


Wow! Can we see ACPI tables for these boards? Care to share (via some
file share service) output of `acpidump -o tables.dat` ?


Please find acpidump [1]. FYI I'm PC Engines firmware maintainer
(firmware is coreboot based), so I can fix required things. I'm pretty
sure that ACPI tables are not in best shape.



Thanks for the dump,

By the way I have seen that the driver
https://github.com/torvalds/linux/blob/master/drivers/gpio/gpio-amdpt.c
is using the acpi to get the mmio address. I think this is the way to go
to get the acpi mmio address in the gpio-apu driver as well.

What is the right "acpi_device_id" for the APU3?
https://github.com/torvalds/linux/blob/master/drivers/gpio/gpio-amdpt.c#L146

Re: [PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs

2018-08-07 Thread Florian Eckert


On 2018-08-03 21:08, Andy Shevchenko wrote:

- APU2/APU3 -> front button reset support
- APU3 -> SIM switch support


Good.
Can we see some specification for those platforms?



I think the informations from Christian Lamparter are OK?







+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see 



SPDX, please!


I have already updated my patch in my git to use this identifier.
// SPDX-License-Identifier: GPL-2.0
This was a hint from Linus Walleji




+ */



+#include 
+#include 


These both looks very strange in here.



On the front of the APU2/APU3 there is a SMD-push-button which is 
connected to
one of the GPIOs. This is used as a reset button for the system 
(reboot/factory-reset).
I am also not sure if this is the right place. But for the first review 
i thought this

will be ok.

The geode, the old board from PC-Engines
added the key gpios to this file
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/platform/geode/alix.c#n47
mybe this is the right place too x86/platfrom/apu/apu.c?


+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)


Wow! Can we see ACPI tables for these boards? Care to share (via some
file share service) output of `acpidump -o tables.dat` ?



I have copied this from the leds-apu.c driver which is already upstream.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/leds/leds-apu.c#n43




+#define APU_GPIO_BIT_WRITE 22
+#define APU_GPIO_BIT_READ  16
+#define APU_GPIO_BIT_DIR   23


WR and RD looks shorter,
And please keep them sorted by value.


Ok will fix this.




+#define APU_IOSIZE sizeof(u32)


This is usual for x86 stuff, no need to have a definition, I think.


Ok will fix this.


+static unsigned long apu3_gpio_offset[APU3_NUM_GPIO] = {
+   APU_FCH_GPIO_BASE + 89 * APU_IOSIZE, //KEY
+   APU_FCH_GPIO_BASE + 90 * APU_IOSIZE, //SIM
+};
+static void __iomem *apu3_gpio_addr[APU3_NUM_GPIO] = {NULL, NULL};
+



+static int gpio_apu_get_dir (struct gpio_chip *chip, unsigned offset)


Style! We do not use space between func and its parameter list.



OK


+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+



+   val = ~ioread32(apu_gpio->addr[offset]);


This is unusual (I mean ~). Better to leave IO alone and do bits
manipulations latter on.


OK




+   val = (val >> APU_GPIO_BIT_DIR) & 1;


Do you need this under spin lock?



No i don´t.
Will fix this.
Thanks


+   apu_gpio->chip->ngpio = ARRAY_SIZE(apu2_gpio_offset);
+   for( i = 0; i < ARRAY_SIZE(apu2_gpio_offset); i++) {
+   apu2_gpio_addr[i] = devm_ioremap(>dev,
+   apu_gpio->offset[i], 
apu_gpio->iosize);

+   if (!apu2_gpio_addr[i]) {
+   return -ENOMEM;
+   }
+   }
+   }


The above should be part either as callback or driver_data of DMI 
entries.


I have copied this from the leds-apu.c driver
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/leds/leds-apu.c#n226




+   ret = gpiochip_add(_apu_chip);


devm_



What do you mean with "devm_"?


+   if (ret) {



+   pr_err("Adding gpiochip failed\n");


dev_err(), but I consider this message completely useless.


Thanks will remove this too.




+   }



+
+   register_gpio_keys_polled(-1, 20, ARRAY_SIZE(apu_gpio_keys), 
apu_gpio_keys);

+


Not part of this driver. Remove.



As described above should this go to a file "apu.c" in the directory 
"apu" under

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/platform
?


+   return ret;
+}



+module_init(apu_gpio_init);
+module_exit(apu_gpio_exit);


Consider to use module_platform_driver() and accompanying data
structures and functions.


Ok thanks will update this


Will update my patch with your hints thanks

Re: [PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs

2018-08-07 Thread Florian Eckert


On 2018-08-03 21:08, Andy Shevchenko wrote:

- APU2/APU3 -> front button reset support
- APU3 -> SIM switch support


Good.
Can we see some specification for those platforms?



I think the informations from Christian Lamparter are OK?







+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see 



SPDX, please!


I have already updated my patch in my git to use this identifier.
// SPDX-License-Identifier: GPL-2.0
This was a hint from Linus Walleji




+ */



+#include 
+#include 


These both looks very strange in here.



On the front of the APU2/APU3 there is a SMD-push-button which is 
connected to
one of the GPIOs. This is used as a reset button for the system 
(reboot/factory-reset).
I am also not sure if this is the right place. But for the first review 
i thought this

will be ok.

The geode, the old board from PC-Engines
added the key gpios to this file
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/platform/geode/alix.c#n47
mybe this is the right place too x86/platfrom/apu/apu.c?


+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)


Wow! Can we see ACPI tables for these boards? Care to share (via some
file share service) output of `acpidump -o tables.dat` ?



I have copied this from the leds-apu.c driver which is already upstream.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/leds/leds-apu.c#n43




+#define APU_GPIO_BIT_WRITE 22
+#define APU_GPIO_BIT_READ  16
+#define APU_GPIO_BIT_DIR   23


WR and RD looks shorter,
And please keep them sorted by value.


Ok will fix this.




+#define APU_IOSIZE sizeof(u32)


This is usual for x86 stuff, no need to have a definition, I think.


Ok will fix this.


+static unsigned long apu3_gpio_offset[APU3_NUM_GPIO] = {
+   APU_FCH_GPIO_BASE + 89 * APU_IOSIZE, //KEY
+   APU_FCH_GPIO_BASE + 90 * APU_IOSIZE, //SIM
+};
+static void __iomem *apu3_gpio_addr[APU3_NUM_GPIO] = {NULL, NULL};
+



+static int gpio_apu_get_dir (struct gpio_chip *chip, unsigned offset)


Style! We do not use space between func and its parameter list.



OK


+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+



+   val = ~ioread32(apu_gpio->addr[offset]);


This is unusual (I mean ~). Better to leave IO alone and do bits
manipulations latter on.


OK




+   val = (val >> APU_GPIO_BIT_DIR) & 1;


Do you need this under spin lock?



No i don´t.
Will fix this.
Thanks


+   apu_gpio->chip->ngpio = ARRAY_SIZE(apu2_gpio_offset);
+   for( i = 0; i < ARRAY_SIZE(apu2_gpio_offset); i++) {
+   apu2_gpio_addr[i] = devm_ioremap(>dev,
+   apu_gpio->offset[i], 
apu_gpio->iosize);

+   if (!apu2_gpio_addr[i]) {
+   return -ENOMEM;
+   }
+   }
+   }


The above should be part either as callback or driver_data of DMI 
entries.


I have copied this from the leds-apu.c driver
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/leds/leds-apu.c#n226




+   ret = gpiochip_add(_apu_chip);


devm_



What do you mean with "devm_"?


+   if (ret) {



+   pr_err("Adding gpiochip failed\n");


dev_err(), but I consider this message completely useless.


Thanks will remove this too.




+   }



+
+   register_gpio_keys_polled(-1, 20, ARRAY_SIZE(apu_gpio_keys), 
apu_gpio_keys);

+


Not part of this driver. Remove.



As described above should this go to a file "apu.c" in the directory 
"apu" under

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/platform
?


+   return ret;
+}



+module_init(apu_gpio_init);
+module_exit(apu_gpio_exit);


Consider to use module_platform_driver() and accompanying data
structures and functions.


Ok thanks will update this


Will update my patch with your hints thanks

Re: [PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs

2018-08-07 Thread Florian Eckert


Hello Andy

I think this are the information you want to have.

On 2018-08-04 20:22, Christian Lamparter wrote:

As for the APUs. The vendor (PC Engines) happily provides
PDFs and schematics for their boards:

Re: [PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs

2018-08-07 Thread Florian Eckert


Hello Andy

I think this are the information you want to have.

On 2018-08-04 20:22, Christian Lamparter wrote:

As for the APUs. The vendor (PC Engines) happily provides
PDFs and schematics for their boards:

[PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs

2018-08-01 Thread Florian Eckert

Add a new device driver "gpio-apu" which will now handle the GPIOs on
APU2 and APU3 devices from PC Engines.

- APU2/APU3 -> front button reset support
- APU3 -> SIM switch support

Signed-off-by: Florian Eckert 
---
 drivers/gpio/Kconfig|  10 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/gpio-apu.c | 344 
 3 files changed, 355 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 71c0ab46f216..9eb8977ba2e5 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -117,6 +117,16 @@ config GPIO_AMDPT
  driver for GPIO functionality on Promontory IOHub
  Require ACPI ASL code to enumerate as a platform device.
 
+config GPIO_APU
+   tristate "PC Engines APU2/APU3 GPIO support"
+   depends on X86
+   select GPIO_GENERIC
+   help
+ Say Y here to support GPIO functionality on APU2/APU3 boards
+ from PC Engines.
+ - APU2/APU3 -> front button reset support
+ - APU3 -> SIM switch support
+
 config GPIO_ASPEED
tristate "Aspeed GPIO support"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 1324c8f966a7..feea4effcf29 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
 obj-$(CONFIG_GPIO_ALTERA_A10SR)+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)   += gpio-amdpt.o
+obj-$(CONFIG_GPIO_APU) += gpio-apu.o
 obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
 obj-$(CONFIG_GPIO_ATH79)   += gpio-ath79.o
 obj-$(CONFIG_GPIO_ASPEED)  += gpio-aspeed.o
diff --git a/drivers/gpio/gpio-apu.c b/drivers/gpio/gpio-apu.c
new file mode 100644
index ..18171c13917a
--- /dev/null
+++ b/drivers/gpio/gpio-apu.c
@@ -0,0 +1,344 @@
+/* PC Engines APU2/APU3 GPIO device driver
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEVNAME"gpio-apu"
+
+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)
+#define APU_GPIO_BIT_WRITE 22
+#define APU_GPIO_BIT_READ  16
+#define APU_GPIO_BIT_DIR   23
+#define APU_IOSIZE sizeof(u32)
+
+#define APU2_NUM_GPIO  1
+#define APU3_NUM_GPIO  2
+
+struct apu_gpio_pdata {
+   struct platform_device *pdev;
+   struct gpio_chip *chip;
+   unsigned long *offset;
+   void __iomem **addr;
+   int iosize; /* for devm_ioremap() */
+   spinlock_t lock;
+};
+
+static struct apu_gpio_pdata *apu_gpio;
+static struct platform_device *keydev;
+
+/* APU2 */
+static unsigned long apu2_gpio_offset[APU2_NUM_GPIO] = {
+   APU_FCH_GPIO_BASE + 89 * APU_IOSIZE, //KEY
+};
+static void __iomem *apu2_gpio_addr[APU2_NUM_GPIO] = {NULL};
+
+/* APU3 */
+static unsigned long apu3_gpio_offset[APU3_NUM_GPIO] = {
+   APU_FCH_GPIO_BASE + 89 * APU_IOSIZE, //KEY
+   APU_FCH_GPIO_BASE + 90 * APU_IOSIZE, //SIM
+};
+static void __iomem *apu3_gpio_addr[APU3_NUM_GPIO] = {NULL, NULL};
+
+static int gpio_apu_get_dir (struct gpio_chip *chip, unsigned offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ~ioread32(apu_gpio->addr[offset]);
+   val = (val >> APU_GPIO_BIT_DIR) & 1;
+
+   spin_unlock(_gpio->lock);
+
+   return val;
+}
+
+static int gpio_apu_dir_in (struct gpio_chip *chip, unsigned offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val &= ~BIT(APU_GPIO_BIT_DIR);
+   iowrite32(val, apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return 0;
+}
+
+static int gpio_apu_dir_out (struct gpio_chip *chip, unsigned offset,
+   int value)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val |= BIT(APU_GPIO_BIT_DIR);
+   iowrite32(val, apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return 0;
+}
+
+sta

[PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs

2018-08-01 Thread Florian Eckert

Add a new device driver "gpio-apu" which will now handle the GPIOs on
APU2 and APU3 devices from PC Engines.

- APU2/APU3 -> front button reset support
- APU3 -> SIM switch support

Signed-off-by: Florian Eckert 
---
 drivers/gpio/Kconfig|  10 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/gpio-apu.c | 344 
 3 files changed, 355 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 71c0ab46f216..9eb8977ba2e5 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -117,6 +117,16 @@ config GPIO_AMDPT
  driver for GPIO functionality on Promontory IOHub
  Require ACPI ASL code to enumerate as a platform device.
 
+config GPIO_APU
+   tristate "PC Engines APU2/APU3 GPIO support"
+   depends on X86
+   select GPIO_GENERIC
+   help
+ Say Y here to support GPIO functionality on APU2/APU3 boards
+ from PC Engines.
+ - APU2/APU3 -> front button reset support
+ - APU3 -> SIM switch support
+
 config GPIO_ASPEED
tristate "Aspeed GPIO support"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 1324c8f966a7..feea4effcf29 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
 obj-$(CONFIG_GPIO_ALTERA_A10SR)+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)   += gpio-amdpt.o
+obj-$(CONFIG_GPIO_APU) += gpio-apu.o
 obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
 obj-$(CONFIG_GPIO_ATH79)   += gpio-ath79.o
 obj-$(CONFIG_GPIO_ASPEED)  += gpio-aspeed.o
diff --git a/drivers/gpio/gpio-apu.c b/drivers/gpio/gpio-apu.c
new file mode 100644
index ..18171c13917a
--- /dev/null
+++ b/drivers/gpio/gpio-apu.c
@@ -0,0 +1,344 @@
+/* PC Engines APU2/APU3 GPIO device driver
+ *
+ * Copyright (C) 2018 Florian Eckert 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DEVNAME"gpio-apu"
+
+#define APU_FCH_ACPI_MMIO_BASE 0xFED8
+#define APU_FCH_GPIO_BASE  (APU_FCH_ACPI_MMIO_BASE + 0x1500)
+#define APU_GPIO_BIT_WRITE 22
+#define APU_GPIO_BIT_READ  16
+#define APU_GPIO_BIT_DIR   23
+#define APU_IOSIZE sizeof(u32)
+
+#define APU2_NUM_GPIO  1
+#define APU3_NUM_GPIO  2
+
+struct apu_gpio_pdata {
+   struct platform_device *pdev;
+   struct gpio_chip *chip;
+   unsigned long *offset;
+   void __iomem **addr;
+   int iosize; /* for devm_ioremap() */
+   spinlock_t lock;
+};
+
+static struct apu_gpio_pdata *apu_gpio;
+static struct platform_device *keydev;
+
+/* APU2 */
+static unsigned long apu2_gpio_offset[APU2_NUM_GPIO] = {
+   APU_FCH_GPIO_BASE + 89 * APU_IOSIZE, //KEY
+};
+static void __iomem *apu2_gpio_addr[APU2_NUM_GPIO] = {NULL};
+
+/* APU3 */
+static unsigned long apu3_gpio_offset[APU3_NUM_GPIO] = {
+   APU_FCH_GPIO_BASE + 89 * APU_IOSIZE, //KEY
+   APU_FCH_GPIO_BASE + 90 * APU_IOSIZE, //SIM
+};
+static void __iomem *apu3_gpio_addr[APU3_NUM_GPIO] = {NULL, NULL};
+
+static int gpio_apu_get_dir (struct gpio_chip *chip, unsigned offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ~ioread32(apu_gpio->addr[offset]);
+   val = (val >> APU_GPIO_BIT_DIR) & 1;
+
+   spin_unlock(_gpio->lock);
+
+   return val;
+}
+
+static int gpio_apu_dir_in (struct gpio_chip *chip, unsigned offset)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val &= ~BIT(APU_GPIO_BIT_DIR);
+   iowrite32(val, apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return 0;
+}
+
+static int gpio_apu_dir_out (struct gpio_chip *chip, unsigned offset,
+   int value)
+{
+   u32 val;
+
+   spin_lock(_gpio->lock);
+
+   val = ioread32(apu_gpio->addr[offset]);
+   val |= BIT(APU_GPIO_BIT_DIR);
+   iowrite32(val, apu_gpio->addr[offset]);
+
+   spin_unlock(_gpio->lock);
+
+   return 0;
+}
+
+sta

[PATCH] leds: add APU3 dmi information to leds-apu

2018-07-30 Thread Florian Eckert

This driver should also get loaded if this is a APU3 from PC Engines.
It has the same pin layout for leds.

Signed-off-by: Florian Eckert 
---
 drivers/leds/leds-apu.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/leds/leds-apu.c b/drivers/leds/leds-apu.c
index 8c93d68964c7..1ed1c5a5dc77 100644
--- a/drivers/leds/leds-apu.c
+++ b/drivers/leds/leds-apu.c
@@ -134,6 +134,14 @@ static const struct dmi_system_id apu_led_dmi_table[] 
__initconst = {
DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
}
},
+   /* PC Engines APU3 with "Legancy" bios >= 4.0.7 */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "APU3")
+   }
+   },
{}
 };
 MODULE_DEVICE_TABLE(dmi, apu_led_dmi_table);
@@ -229,6 +237,7 @@ static int __init apu_led_probe(struct platform_device 
*pdev)
apu_led->num_led_instances = ARRAY_SIZE(apu1_led_profile);
apu_led->iosize = APU1_IOSIZE;
} else if (dmi_match(DMI_BOARD_NAME, "APU2") ||
+  dmi_match(DMI_BOARD_NAME, "APU3") ||
   dmi_match(DMI_BOARD_NAME, "apu2") ||
   dmi_match(DMI_BOARD_NAME, "PC Engines apu2")) {
apu_led->profile = apu2_led_profile;
@@ -258,6 +267,7 @@ static int __init apu_led_init(void)
}
if (!(dmi_match(DMI_PRODUCT_NAME, "APU") ||
  dmi_match(DMI_PRODUCT_NAME, "APU2") ||
+ dmi_match(DMI_PRODUCT_NAME, "APU3") ||
  dmi_match(DMI_PRODUCT_NAME, "apu2") ||
  dmi_match(DMI_PRODUCT_NAME, "PC Engines apu2"))) {
pr_err("Unknown PC Engines board: %s\n",
-- 
2.11.0

[PATCH] leds: add APU3 dmi information to leds-apu

2018-07-30 Thread Florian Eckert

This driver should also get loaded if this is a APU3 from PC Engines.
It has the same pin layout for leds.

Signed-off-by: Florian Eckert 
---
 drivers/leds/leds-apu.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/leds/leds-apu.c b/drivers/leds/leds-apu.c
index 8c93d68964c7..1ed1c5a5dc77 100644
--- a/drivers/leds/leds-apu.c
+++ b/drivers/leds/leds-apu.c
@@ -134,6 +134,14 @@ static const struct dmi_system_id apu_led_dmi_table[] 
__initconst = {
DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
}
},
+   /* PC Engines APU3 with "Legancy" bios >= 4.0.7 */
+   {
+   .ident = "apu3",
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+   DMI_MATCH(DMI_BOARD_NAME, "APU3")
+   }
+   },
{}
 };
 MODULE_DEVICE_TABLE(dmi, apu_led_dmi_table);
@@ -229,6 +237,7 @@ static int __init apu_led_probe(struct platform_device 
*pdev)
apu_led->num_led_instances = ARRAY_SIZE(apu1_led_profile);
apu_led->iosize = APU1_IOSIZE;
} else if (dmi_match(DMI_BOARD_NAME, "APU2") ||
+  dmi_match(DMI_BOARD_NAME, "APU3") ||
   dmi_match(DMI_BOARD_NAME, "apu2") ||
   dmi_match(DMI_BOARD_NAME, "PC Engines apu2")) {
apu_led->profile = apu2_led_profile;
@@ -258,6 +267,7 @@ static int __init apu_led_init(void)
}
if (!(dmi_match(DMI_PRODUCT_NAME, "APU") ||
  dmi_match(DMI_PRODUCT_NAME, "APU2") ||
+ dmi_match(DMI_PRODUCT_NAME, "APU3") ||
  dmi_match(DMI_PRODUCT_NAME, "apu2") ||
  dmi_match(DMI_PRODUCT_NAME, "PC Engines apu2"))) {
pr_err("Unknown PC Engines board: %s\n",
-- 
2.11.0

Re: [PATCH v3 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-09-14 Thread Florian Eckert


Hello Rob


> +
> +Requires node properties:
> +- compatible value :
> + "lantiq,cputemp"



Kind of non-specific. How is this device even accessed without any 
other

property?



It does not need any further properties. If this is set in the device 
tree

then the driver is loaded.


DT is not the only way to instantiate drivers.

What I meant is how do you access the hardware? That should be evident
from the binding and it is not.


Agree with our statement.



Looking at the driver, you have some memory mapped system control
registers which get ioremapped in arch/mips/lantiq/xway/sysctrl.c and
accesses thru some platform specific macros. That is not the ideal way
to do things as we use syscon and regmap for such things. But that's
all mostly kernel details not so relevant to the DT binding.


For lanitq xrx200 this is all i have. So if i have to use syscon and 
regmap i am also not sure how to handle this.



For DT, I'd expect this is a child node of the sysctrl block with a
reg property value of <0x40 4> (along with any other child devices).
You could also not even put this in DT and the system controller can
have it's own driver that instantiates the child device for this
driver.


Yes this would be the best practice. But the hardware designer for what 
ever reason
placed the Register for the temperature sensors into the CGU (Clock 
Generation Unit) section!
And the Register is also shared with some other stuff which is not only 
assign for temperature

stuff! I am not sure how to handle this in the device tree.

This is a Register description extract from the data sheet

GPHY Configuration Register 01
This register configures the booting options of GPHY1 IP.

Offset 0x0040
Reset Value 0x01FC

31: RES
30: 100FX_H
29: 100FX_F
28: 10BT_F
27: 10BT_H
26: 100BT_F
25: 100BT_H
24: 1000BT_F
23: 1000BT_H
22: RES
21: RES
19: TEMP_PD <--- NEEDED Power down the Temperature Sensor
18: TEMP_HL <--- NEEDED Indicate temperature higher than 128 C
17: TEMP<--- NEEDED Value
16: TEMP<--- NEEDED Value
15: TEMP<--- NEEDED Value
14: TEMP<--- NEEDED Value
13: TEMP<--- NEEDED Value
12: TEMP<--- NEEDED Value
11: TEMP<--- NEEDED Value
10: TEMP<--- NEEDED Value
09: TEMP<--- NEEDED Value
08: RES
07: RES
06: SPI_Delay
05: SPI_Delay
04: AHB_EnD
03: DMA_OR
02: RES
01: RES
00: RES

And that is a dts tree from LEDE/Openwrt for lantiq
URL:
https://github.com/lede-project/source/blob/c88770c766fdc5599efc4672bca230017f52e8e4/target/linux/lantiq/dts/vr9.dtsi#L54

Extraction:
sram@1F00 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,sram", "simple-bus";
reg = <0x1F00 0x80>;
ranges = <0x0 0x1F00 0x7F>;

eiu0: eiu@101000 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "lantiq,eiu-xway";
reg = <0x101000 0x1000>;
interrupt-parent = <>;
lantiq,eiu-irqs = <166 135 66 40 41 42>;
};

pmu0: pmu@102000 {
compatible = "lantiq,pmu-xway";
reg = <0x102000 0x1000>;
};

cgu0: cgu@103000 {
compatible = "lantiq,cgu-xway";
reg = <0x103000 0x1000>;
-> This is the place to add the binding?
};

Sorry for the noise but i am unsure how to do this.
Thanks for help

Florian

Re: [PATCH v3 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-09-14 Thread Florian Eckert


Hello Rob


> +
> +Requires node properties:
> +- compatible value :
> + "lantiq,cputemp"



Kind of non-specific. How is this device even accessed without any 
other

property?



It does not need any further properties. If this is set in the device 
tree

then the driver is loaded.


DT is not the only way to instantiate drivers.

What I meant is how do you access the hardware? That should be evident
from the binding and it is not.


Agree with our statement.



Looking at the driver, you have some memory mapped system control
registers which get ioremapped in arch/mips/lantiq/xway/sysctrl.c and
accesses thru some platform specific macros. That is not the ideal way
to do things as we use syscon and regmap for such things. But that's
all mostly kernel details not so relevant to the DT binding.


For lanitq xrx200 this is all i have. So if i have to use syscon and 
regmap i am also not sure how to handle this.



For DT, I'd expect this is a child node of the sysctrl block with a
reg property value of <0x40 4> (along with any other child devices).
You could also not even put this in DT and the system controller can
have it's own driver that instantiates the child device for this
driver.


Yes this would be the best practice. But the hardware designer for what 
ever reason
placed the Register for the temperature sensors into the CGU (Clock 
Generation Unit) section!
And the Register is also shared with some other stuff which is not only 
assign for temperature

stuff! I am not sure how to handle this in the device tree.

This is a Register description extract from the data sheet

GPHY Configuration Register 01
This register configures the booting options of GPHY1 IP.

Offset 0x0040
Reset Value 0x01FC

31: RES
30: 100FX_H
29: 100FX_F
28: 10BT_F
27: 10BT_H
26: 100BT_F
25: 100BT_H
24: 1000BT_F
23: 1000BT_H
22: RES
21: RES
19: TEMP_PD <--- NEEDED Power down the Temperature Sensor
18: TEMP_HL <--- NEEDED Indicate temperature higher than 128 C
17: TEMP<--- NEEDED Value
16: TEMP<--- NEEDED Value
15: TEMP<--- NEEDED Value
14: TEMP<--- NEEDED Value
13: TEMP<--- NEEDED Value
12: TEMP<--- NEEDED Value
11: TEMP<--- NEEDED Value
10: TEMP<--- NEEDED Value
09: TEMP<--- NEEDED Value
08: RES
07: RES
06: SPI_Delay
05: SPI_Delay
04: AHB_EnD
03: DMA_OR
02: RES
01: RES
00: RES

And that is a dts tree from LEDE/Openwrt for lantiq
URL:
https://github.com/lede-project/source/blob/c88770c766fdc5599efc4672bca230017f52e8e4/target/linux/lantiq/dts/vr9.dtsi#L54

Extraction:
sram@1F00 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,sram", "simple-bus";
reg = <0x1F00 0x80>;
ranges = <0x0 0x1F00 0x7F>;

eiu0: eiu@101000 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "lantiq,eiu-xway";
reg = <0x101000 0x1000>;
interrupt-parent = <>;
lantiq,eiu-irqs = <166 135 66 40 41 42>;
};

pmu0: pmu@102000 {
compatible = "lantiq,pmu-xway";
reg = <0x102000 0x1000>;
};

cgu0: cgu@103000 {
compatible = "lantiq,cgu-xway";
reg = <0x103000 0x1000>;
-> This is the place to add the binding?
};

Sorry for the noise but i am unsure how to do this.
Thanks for help

Florian

Re: [PATCH v3 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-09-13 Thread Florian Eckert


>
>>> +
>>> +Requires node properties:
>>> +- compatible value :
>>> +  "lantiq,cputemp"
>
>Kind of non-specific. How is this device even accessed without any other
>property?

It does not need any further properties. If this is set in the device 
tree

then the driver is loaded.
After loading the temperature could be read from "/sys/class/hwmon".
Let me know what should i do to get this fixed?



What about with this is this OK from your side or do I have do to 
something?
So I only update "s/temperatur/temperature/" with an follow-up patch 
based the current linux-next tree?


Thanks

Florian

Re: [PATCH v3 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-09-13 Thread Florian Eckert


>
>>> +
>>> +Requires node properties:
>>> +- compatible value :
>>> +  "lantiq,cputemp"
>
>Kind of non-specific. How is this device even accessed without any other
>property?

It does not need any further properties. If this is set in the device 
tree

then the driver is loaded.
After loading the temperature could be read from "/sys/class/hwmon".
Let me know what should i do to get this fixed?



What about with this is this OK from your side or do I have do to 
something?
So I only update "s/temperatur/temperature/" with an follow-up patch 
based the current linux-next tree?


Thanks

Florian

Re: [PATCH v3 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-09-12 Thread Florian Eckert


Hello Rob


> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
> @@ -0,0 +1,10 @@
> +Lantiq cpu temperatur sensor


s/temperatur/temperature/


Will update this in a follow up page based on the old one. So no v4?




> +
> +Requires node properties:
> +- compatible value :
> +  "lantiq,cputemp"


Kind of non-specific. How is this device even accessed without any 
other

property?


It does not need any further properties. If this is set in the device 
tree then the driver is loaded.

After loading the temperature could be read from "/sys/class/hwmon".

Let me know what should i do to get this fixed?

Thanks for feedback

Florian

Re: [PATCH v3 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-09-12 Thread Florian Eckert


Hello Rob


> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
> @@ -0,0 +1,10 @@
> +Lantiq cpu temperatur sensor


s/temperatur/temperature/


Will update this in a follow up page based on the old one. So no v4?




> +
> +Requires node properties:
> +- compatible value :
> +  "lantiq,cputemp"


Kind of non-specific. How is this device even accessed without any 
other

property?


It does not need any further properties. If this is set in the device 
tree then the driver is loaded.

After loading the temperature could be read from "/sys/class/hwmon".

Let me know what should i do to get this fixed?

Thanks for feedback

Florian

Re: [v2,1/2] hwmon: (adcxx) add devictree bindings documentation

2017-09-04 Thread Florian Eckert


Hello Guenter

Thank you again for reviewing my patches!
It was the first time for me :-) to add something to the kernel.


+- vref-supply
+  The external reference in microvolt for this device is set to this 
value.
+  If it does not exists the reference will be set to 330uV 
(3.3V).


s/exists/exist/



Sorry for the noise and thank you for the hint.


+
+Example:
+
+adc@6 {
+   compatible = "national,adcxx2s";
+   reg = <6 0>;
+   spi-max-frequency = <100>;


I asssume that means that standard spi properties are accepted / 
required,

which I think should be documented. We'll need input from Rob for that.


Yes this is a standard option.
I have added this because 
"Documentation/devicetree/bindings/hwmon/lm70.txt"

did the same. This was my pattern.

I will send a follow up patch set if this is clarivied. Let me know if 
this is needed or not.


Thanks
Florian

Re: [v2,1/2] hwmon: (adcxx) add devictree bindings documentation

2017-09-04 Thread Florian Eckert


Hello Guenter

Thank you again for reviewing my patches!
It was the first time for me :-) to add something to the kernel.


+- vref-supply
+  The external reference in microvolt for this device is set to this 
value.
+  If it does not exists the reference will be set to 330uV 
(3.3V).


s/exists/exist/



Sorry for the noise and thank you for the hint.


+
+Example:
+
+adc@6 {
+   compatible = "national,adcxx2s";
+   reg = <6 0>;
+   spi-max-frequency = <100>;


I asssume that means that standard spi properties are accepted / 
required,

which I think should be documented. We'll need input from Rob for that.


Yes this is a standard option.
I have added this because 
"Documentation/devicetree/bindings/hwmon/lm70.txt"

did the same. This was my pattern.

I will send a follow up patch set if this is clarivied. Let me know if 
this is needed or not.


Thanks
Florian

[PATCH v3 1/2] hwmon: (ltq-cputemp) add cpu temp sensor driver

2017-09-01 Thread Florian Eckert

Add the lantiq cpu temperature sensor support for xrx200.

Signed-off-by: Florian Eckert <f...@dev.tdt.de>
---
v2:
- remove default in Makefile
- fix spelling
- removing first read delay, because temperature value is not read during boot
  anymore
- change calculation, compiler should to the optimization
- remove unnecessary initialization
- use new devm_hwmon_device_register_with_info API
- use module_platform_driver function

v3:
- sort includes in alphabetic order
- add missing linux/bitops.h include
- fix alignment
- fix switch case indentation
- use octal file permission instead of S_IRUGO
- set hwmon device name to "ltq_cputemp"
- enable temperature chip before hwmon registration
- remove release function registrate ltq_cputemp_disable()
  with devm_add_action
- remove init_ltq_cputemp and clean_ltq_cputemp not used
  overlooked it on v2

 drivers/hwmon/Kconfig   |   7 ++
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/ltq-cputemp.c | 163 
 3 files changed, 171 insertions(+)
 create mode 100644 drivers/hwmon/ltq-cputemp.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 5ef2814345ef..218332f0e913 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -790,6 +790,13 @@ config SENSORS_LTC4261
  This driver can also be built as a module. If so, the module will
  be called ltc4261.
 
+config SENSORS_LTQ_CPUTEMP
+   bool "Lantiq cpu temperature sensor driver"
+   depends on LANTIQ
+   help
+ If you say yes here you get support for the temperature
+ sensor inside your CPU.
+
 config SENSORS_MAX
tristate "Maxim MAX Serial 8-bit ADC chip and compatibles"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index d4641a9f16c1..c84d9784be98 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_SENSORS_LTC4222)   += ltc4222.o
 obj-$(CONFIG_SENSORS_LTC4245)  += ltc4245.o
 obj-$(CONFIG_SENSORS_LTC4260)  += ltc4260.o
 obj-$(CONFIG_SENSORS_LTC4261)  += ltc4261.o
+obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o
 obj-$(CONFIG_SENSORS_MAX)  += max.o
 obj-$(CONFIG_SENSORS_MAX16065) += max16065.o
 obj-$(CONFIG_SENSORS_MAX1619)  += max1619.o
diff --git a/drivers/hwmon/ltq-cputemp.c b/drivers/hwmon/ltq-cputemp.c
new file mode 100644
index ..1d33f94594c1
--- /dev/null
+++ b/drivers/hwmon/ltq-cputemp.c
@@ -0,0 +1,163 @@
+/* Lantiq cpu temperature sensor driver
+ *
+ * Copyright (C) 2017 Florian Eckert <f...@dev.tdt.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/* gphy1 configuration register contains cpu temperature */
+#define CGU_GPHY1_CR   0x0040
+#define CGU_TEMP_PDBIT(19)
+
+static void ltq_cputemp_enable(void)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static void ltq_cputemp_disable(void *data)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static int ltq_read(struct device *dev, enum hwmon_sensor_types type,
+   u32 attr, int channel, long *temp)
+{
+   int value;
+
+   switch (attr) {
+   case hwmon_temp_input:
+   /* get the temperature including one decimal place */
+   value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF;
+   value = value * 5;
+   /* range -38 to +154 °C, register value zero is -38.0 °C */
+   value -= 380;
+   /* scale temp to millidegree */
+   value = value * 100;
+   break;
+   default:
+   return -EOPNOTSUPP;
+   }
+
+   *temp = value;
+   return 0;
+}
+
+static umode_t ltq_is_visible(const void *_data, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+   if (type != hwmon_temp)
+   return 0;
+
+   switch (attr) {
+   case hwmon_temp_input:
+   return 0444;
+   default:
+   return 0;
+   }
+}
+
+static const u32 ltq_chip_config[] = {
+   HWMON_C_REGISTER_TZ,
+   0
+};
+
+static const struct hwmon_channel_info ltq_chip = {
+   .type = hwmon_ch

[PATCH v3 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-09-01 Thread Florian Eckert

Document the devicetree bindings for the ltq-cputemp

Signed-off-by: Florian Eckert <f...@dev.tdt.de>
---
 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt | 10 ++
 1 file changed, 10 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt

diff --git a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt 
b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
new file mode 100644
index ..33fd00a987c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
@@ -0,0 +1,10 @@
+Lantiq cpu temperatur sensor
+
+Requires node properties:
+- compatible value :
+   "lantiq,cputemp"
+
+Example:
+   cputemp@0 {
+   compatible = "lantiq,cputemp";
+   };
-- 
2.11.0

[PATCH v3 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-09-01 Thread Florian Eckert

Document the devicetree bindings for the ltq-cputemp

Signed-off-by: Florian Eckert 
---
 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt | 10 ++
 1 file changed, 10 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt

diff --git a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt 
b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
new file mode 100644
index ..33fd00a987c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
@@ -0,0 +1,10 @@
+Lantiq cpu temperatur sensor
+
+Requires node properties:
+- compatible value :
+   "lantiq,cputemp"
+
+Example:
+   cputemp@0 {
+   compatible = "lantiq,cputemp";
+   };
-- 
2.11.0

[PATCH v3 1/2] hwmon: (ltq-cputemp) add cpu temp sensor driver

2017-09-01 Thread Florian Eckert

Add the lantiq cpu temperature sensor support for xrx200.

Signed-off-by: Florian Eckert 
---
v2:
- remove default in Makefile
- fix spelling
- removing first read delay, because temperature value is not read during boot
  anymore
- change calculation, compiler should to the optimization
- remove unnecessary initialization
- use new devm_hwmon_device_register_with_info API
- use module_platform_driver function

v3:
- sort includes in alphabetic order
- add missing linux/bitops.h include
- fix alignment
- fix switch case indentation
- use octal file permission instead of S_IRUGO
- set hwmon device name to "ltq_cputemp"
- enable temperature chip before hwmon registration
- remove release function registrate ltq_cputemp_disable()
  with devm_add_action
- remove init_ltq_cputemp and clean_ltq_cputemp not used
  overlooked it on v2

 drivers/hwmon/Kconfig   |   7 ++
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/ltq-cputemp.c | 163 
 3 files changed, 171 insertions(+)
 create mode 100644 drivers/hwmon/ltq-cputemp.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 5ef2814345ef..218332f0e913 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -790,6 +790,13 @@ config SENSORS_LTC4261
  This driver can also be built as a module. If so, the module will
  be called ltc4261.
 
+config SENSORS_LTQ_CPUTEMP
+   bool "Lantiq cpu temperature sensor driver"
+   depends on LANTIQ
+   help
+ If you say yes here you get support for the temperature
+ sensor inside your CPU.
+
 config SENSORS_MAX
tristate "Maxim MAX Serial 8-bit ADC chip and compatibles"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index d4641a9f16c1..c84d9784be98 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_SENSORS_LTC4222)   += ltc4222.o
 obj-$(CONFIG_SENSORS_LTC4245)  += ltc4245.o
 obj-$(CONFIG_SENSORS_LTC4260)  += ltc4260.o
 obj-$(CONFIG_SENSORS_LTC4261)  += ltc4261.o
+obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o
 obj-$(CONFIG_SENSORS_MAX)  += max.o
 obj-$(CONFIG_SENSORS_MAX16065) += max16065.o
 obj-$(CONFIG_SENSORS_MAX1619)  += max1619.o
diff --git a/drivers/hwmon/ltq-cputemp.c b/drivers/hwmon/ltq-cputemp.c
new file mode 100644
index ..1d33f94594c1
--- /dev/null
+++ b/drivers/hwmon/ltq-cputemp.c
@@ -0,0 +1,163 @@
+/* Lantiq cpu temperature sensor driver
+ *
+ * Copyright (C) 2017 Florian Eckert 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/* gphy1 configuration register contains cpu temperature */
+#define CGU_GPHY1_CR   0x0040
+#define CGU_TEMP_PDBIT(19)
+
+static void ltq_cputemp_enable(void)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static void ltq_cputemp_disable(void *data)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static int ltq_read(struct device *dev, enum hwmon_sensor_types type,
+   u32 attr, int channel, long *temp)
+{
+   int value;
+
+   switch (attr) {
+   case hwmon_temp_input:
+   /* get the temperature including one decimal place */
+   value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF;
+   value = value * 5;
+   /* range -38 to +154 °C, register value zero is -38.0 °C */
+   value -= 380;
+   /* scale temp to millidegree */
+   value = value * 100;
+   break;
+   default:
+   return -EOPNOTSUPP;
+   }
+
+   *temp = value;
+   return 0;
+}
+
+static umode_t ltq_is_visible(const void *_data, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+   if (type != hwmon_temp)
+   return 0;
+
+   switch (attr) {
+   case hwmon_temp_input:
+   return 0444;
+   default:
+   return 0;
+   }
+}
+
+static const u32 ltq_chip_config[] = {
+   HWMON_C_REGISTER_TZ,
+   0
+};
+
+static const struct hwmon_channel_info ltq_chip = {
+   .type = hwmon_chip,
+   .config = ltq_ch

[PATCH v2 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-08-21 Thread Florian Eckert

Document the devicetree bindings for the ltq-cputemp

Signed-off-by: Florian Eckert <f...@dev.tdt.de>
---
 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt | 10 ++
 1 file changed, 10 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt

diff --git a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt 
b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
new file mode 100644
index ..991b05cbcb4a
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
@@ -0,0 +1,10 @@
+Lantiq cpu temperatur sensor driver
+
+Requires node properties:
+- "compatible" value :
+   "lantiq,cputemp"
+
+Example:
+   cputemp@0 {
+   compatible = "lantiq,cputemp";
+   };
-- 
2.11.0

[PATCH v2 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-08-21 Thread Florian Eckert

Document the devicetree bindings for the ltq-cputemp

Signed-off-by: Florian Eckert 
---
 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt | 10 ++
 1 file changed, 10 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt

diff --git a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt 
b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
new file mode 100644
index ..991b05cbcb4a
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
@@ -0,0 +1,10 @@
+Lantiq cpu temperatur sensor driver
+
+Requires node properties:
+- "compatible" value :
+   "lantiq,cputemp"
+
+Example:
+   cputemp@0 {
+   compatible = "lantiq,cputemp";
+   };
-- 
2.11.0

[PATCH v2 1/2] hwmon: (ltq-cputemp) add cpu temp sensor driver

2017-08-21 Thread Florian Eckert

Add the lantiq cpu temperature sensor support for xrx200.

Signed-off-by: Florian Eckert <f...@dev.tdt.de>
---
v2:
- remove default in Makefile
- fix spelling
- removing first read delay, because temperature value is not read during boot
  anymore
- change calculation, compiler should to the optimization
- remove unnecessary initialization
- use new devm_hwmon_device_register_with_info API
- use module_platform_driver function

The soc detection for lantiq is done with this pattern. If it sould be more
generic we should change this global.

 drivers/hwmon/Kconfig   |   7 ++
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/ltq-cputemp.c | 175 
 3 files changed, 183 insertions(+)
 create mode 100644 drivers/hwmon/ltq-cputemp.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 5ef2814345ef..218332f0e913 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -790,6 +790,13 @@ config SENSORS_LTC4261
  This driver can also be built as a module. If so, the module will
  be called ltc4261.
 
+config SENSORS_LTQ_CPUTEMP
+   bool "Lantiq cpu temperature sensor driver"
+   depends on LANTIQ
+   help
+ If you say yes here you get support for the temperature
+ sensor inside your CPU.
+
 config SENSORS_MAX
tristate "Maxim MAX Serial 8-bit ADC chip and compatibles"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index d4641a9f16c1..c84d9784be98 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_SENSORS_LTC4222)   += ltc4222.o
 obj-$(CONFIG_SENSORS_LTC4245)  += ltc4245.o
 obj-$(CONFIG_SENSORS_LTC4260)  += ltc4260.o
 obj-$(CONFIG_SENSORS_LTC4261)  += ltc4261.o
+obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o
 obj-$(CONFIG_SENSORS_MAX)  += max.o
 obj-$(CONFIG_SENSORS_MAX16065) += max16065.o
 obj-$(CONFIG_SENSORS_MAX1619)  += max1619.o
diff --git a/drivers/hwmon/ltq-cputemp.c b/drivers/hwmon/ltq-cputemp.c
new file mode 100644
index ..21c77a125c27
--- /dev/null
+++ b/drivers/hwmon/ltq-cputemp.c
@@ -0,0 +1,175 @@
+/* Lantiq cpu temperature sensor driver
+ *
+ * Copyright (C) 2017 Florian Eckert <f...@dev.tdt.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/* gphy1 configuration register contains cpu temperature */
+#define CGU_GPHY1_CR   0x0040
+#define CGU_TEMP_PDBIT(19)
+
+static void ltq_cputemp_enable(void)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static void ltq_cputemp_disable(void)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static int ltq_read(struct device *dev, enum hwmon_sensor_types type,
+   u32 attr, int channel, long *temp)
+{
+   int value;
+
+   switch (attr) {
+   case hwmon_temp_input:
+   /* get the temperature including one decimal place */
+   value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF;
+   value = value * 5;
+   /* range -38 to +154 °C, register value zero is -38.0 °C */
+   value -= 380;
+   /* scale temp to millidegree */
+   value = value * 100;
+   break;
+   default:
+   return -EOPNOTSUPP;
+   }
+
+   *temp = value;
+   return 0;
+}
+
+
+static umode_t ltq_is_visible(const void *_data, enum hwmon_sensor_types type,
+   u32 attr, int channel)
+{
+   if (type != hwmon_temp)
+   return 0;
+
+   switch (attr) {
+   case hwmon_temp_input:
+   return S_IRUGO;
+   default:
+   return 0;
+   }
+}
+
+static const u32 ltq_chip_config[] = {
+   HWMON_C_REGISTER_TZ,
+   0
+};
+
+static const struct hwmon_channel_info ltq_chip = {
+   .type = hwmon_chip,
+   .config = ltq_chip_config,
+};
+
+static const u32 ltq_temp_config[] = {
+   HWMON_T_INPUT,
+   0
+};
+
+static const struct hwmon_channel_info ltq_temp = {
+   .type = hwmon_temp,
+   .config = ltq_temp_config,
+};
+
+static const struct hwmon_channel_info *ltq_info[] = {
+   _chip,
+   _tem

[PATCH v2 1/2] hwmon: (ltq-cputemp) add cpu temp sensor driver

2017-08-21 Thread Florian Eckert

Add the lantiq cpu temperature sensor support for xrx200.

Signed-off-by: Florian Eckert 
---
v2:
- remove default in Makefile
- fix spelling
- removing first read delay, because temperature value is not read during boot
  anymore
- change calculation, compiler should to the optimization
- remove unnecessary initialization
- use new devm_hwmon_device_register_with_info API
- use module_platform_driver function

The soc detection for lantiq is done with this pattern. If it sould be more
generic we should change this global.

 drivers/hwmon/Kconfig   |   7 ++
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/ltq-cputemp.c | 175 
 3 files changed, 183 insertions(+)
 create mode 100644 drivers/hwmon/ltq-cputemp.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 5ef2814345ef..218332f0e913 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -790,6 +790,13 @@ config SENSORS_LTC4261
  This driver can also be built as a module. If so, the module will
  be called ltc4261.
 
+config SENSORS_LTQ_CPUTEMP
+   bool "Lantiq cpu temperature sensor driver"
+   depends on LANTIQ
+   help
+ If you say yes here you get support for the temperature
+ sensor inside your CPU.
+
 config SENSORS_MAX
tristate "Maxim MAX Serial 8-bit ADC chip and compatibles"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index d4641a9f16c1..c84d9784be98 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_SENSORS_LTC4222)   += ltc4222.o
 obj-$(CONFIG_SENSORS_LTC4245)  += ltc4245.o
 obj-$(CONFIG_SENSORS_LTC4260)  += ltc4260.o
 obj-$(CONFIG_SENSORS_LTC4261)  += ltc4261.o
+obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o
 obj-$(CONFIG_SENSORS_MAX)  += max.o
 obj-$(CONFIG_SENSORS_MAX16065) += max16065.o
 obj-$(CONFIG_SENSORS_MAX1619)  += max1619.o
diff --git a/drivers/hwmon/ltq-cputemp.c b/drivers/hwmon/ltq-cputemp.c
new file mode 100644
index ..21c77a125c27
--- /dev/null
+++ b/drivers/hwmon/ltq-cputemp.c
@@ -0,0 +1,175 @@
+/* Lantiq cpu temperature sensor driver
+ *
+ * Copyright (C) 2017 Florian Eckert 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/* gphy1 configuration register contains cpu temperature */
+#define CGU_GPHY1_CR   0x0040
+#define CGU_TEMP_PDBIT(19)
+
+static void ltq_cputemp_enable(void)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static void ltq_cputemp_disable(void)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static int ltq_read(struct device *dev, enum hwmon_sensor_types type,
+   u32 attr, int channel, long *temp)
+{
+   int value;
+
+   switch (attr) {
+   case hwmon_temp_input:
+   /* get the temperature including one decimal place */
+   value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF;
+   value = value * 5;
+   /* range -38 to +154 °C, register value zero is -38.0 °C */
+   value -= 380;
+   /* scale temp to millidegree */
+   value = value * 100;
+   break;
+   default:
+   return -EOPNOTSUPP;
+   }
+
+   *temp = value;
+   return 0;
+}
+
+
+static umode_t ltq_is_visible(const void *_data, enum hwmon_sensor_types type,
+   u32 attr, int channel)
+{
+   if (type != hwmon_temp)
+   return 0;
+
+   switch (attr) {
+   case hwmon_temp_input:
+   return S_IRUGO;
+   default:
+   return 0;
+   }
+}
+
+static const u32 ltq_chip_config[] = {
+   HWMON_C_REGISTER_TZ,
+   0
+};
+
+static const struct hwmon_channel_info ltq_chip = {
+   .type = hwmon_chip,
+   .config = ltq_chip_config,
+};
+
+static const u32 ltq_temp_config[] = {
+   HWMON_T_INPUT,
+   0
+};
+
+static const struct hwmon_channel_info ltq_temp = {
+   .type = hwmon_temp,
+   .config = ltq_temp_config,
+};
+
+static const struct hwmon_channel_info *ltq_info[] = {
+   _chip,
+   _temp,
+   NULL
+};
+
+static const struct hwmon_o

[PATCH v2 2/2] hwmon: (adcxx) Add device tree support

2017-08-21 Thread Florian Eckert

Add device tree supoort for this driver.
Set reference voltage of ADC with the regulator device tree property.
If not set use default 330uV (3.3V).

- vref-supply

Signed-off-by: Florian Eckert <f...@dev.tdt.de>
---
v2:
- use regulator voltage binding
- use dev_dbg
 drivers/hwmon/adcxx.c | 62 +--
 1 file changed, 55 insertions(+), 7 deletions(-)

diff --git a/drivers/hwmon/adcxx.c b/drivers/hwmon/adcxx.c
index 69e0bb97e597..6f3e7d65b5b8 100644
--- a/drivers/hwmon/adcxx.c
+++ b/drivers/hwmon/adcxx.c
@@ -4,6 +4,7 @@
  * The adcxx4s is an AD converter family from National Semiconductor (NS).
  *
  * Copyright (c) 2008 Marc Pignat <marc.pig...@hevs.ch>
+ * Copyright (c) 2017 Florian Eckert <f...@dev.tdt.de>
  *
  * The adcxx4s communicates with a host processor via an SPI/Microwire Bus
  * interface. This driver supports the whole family of devices with name
@@ -46,9 +47,16 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #define DRVNAME"adcxx"
 
+#define ADCXX1S  1
+#define ADCXX2S  2
+#define ADCXX4S  4
+#define ADCXX8S  8
+
 struct adcxx {
struct device *hwmon_dev;
struct mutex lock;
@@ -159,21 +167,60 @@ static struct sensor_device_attribute ad_input[] = {
SENSOR_ATTR(in7_input, S_IRUGO, adcxx_read, NULL, 7),
 };
 
+#ifdef CONFIG_OF
+static const struct of_device_id adcxx_of_ids[] = {
+   {
+   .compatible = "national,adcxx1s",
+   .data = (void *) ADCXX1S,
+   },
+   {
+   .compatible = "national,adcxx2s",
+   .data = (void *) ADCXX2S,
+   },
+   {
+   .compatible = "national,adcxx4s",
+   .data = (void *) ADCXX4S,
+   },
+   {
+   .compatible = "national,adcxx8s",
+   .   data = (void *) ADCXX8S,
+   },
+   {},
+};
+MODULE_DEVICE_TABLE(of, adcxx_of_ids);
+#endif
+
 /*--*/
 
 static int adcxx_probe(struct spi_device *spi)
 {
-   int channels = spi_get_device_id(spi)->driver_data;
+   const struct of_device_id *match;
+   struct regulator *vref;
+   int vref_uv;
+   int channels;
struct adcxx *adc;
int status;
int i;
 
+   match = of_match_device(adcxx_of_ids, >dev);
+   if (match)
+   channels = (int)(uintptr_t)match->data;
+   else
+   channels = spi_get_device_id(spi)->driver_data;
+
adc = devm_kzalloc(>dev, sizeof(*adc), GFP_KERNEL);
if (!adc)
return -ENOMEM;
 
-   /* set a default value for the reference */
-   adc->reference = 3300;
+   vref = devm_regulator_get_optional(>dev, "vref");
+   if (!IS_ERR(vref)) {
+   vref_uv = regulator_get_voltage(vref);
+   adc->reference = DIV_ROUND_CLOSEST(vref_uv, 1000);
+   }
+   if (!adc->reference)
+   adc->reference = 3300;
+   dev_dbg(>dev, "Reference voltage set to %dmV\n", adc->reference);
+
adc->channels = channels;
mutex_init(>lock);
 
@@ -223,10 +270,10 @@ static int adcxx_remove(struct spi_device *spi)
 }
 
 static const struct spi_device_id adcxx_ids[] = {
-   { "adcxx1s", 1 },
-   { "adcxx2s", 2 },
-   { "adcxx4s", 4 },
-   { "adcxx8s", 8 },
+   { "adcxx1s", ADCXX1S },
+   { "adcxx2s", ADCXX2S },
+   { "adcxx4s", ADCXX4S },
+   { "adcxx8s", ADCXX8S },
{ },
 };
 MODULE_DEVICE_TABLE(spi, adcxx_ids);
@@ -234,6 +281,7 @@ MODULE_DEVICE_TABLE(spi, adcxx_ids);
 static struct spi_driver adcxx_driver = {
.driver = {
.name   = "adcxx",
+   .of_match_table = of_match_ptr(adcxx_of_ids),
},
.id_table = adcxx_ids,
.probe  = adcxx_probe,
-- 
2.11.0

[PATCH v2 2/2] hwmon: (adcxx) Add device tree support

2017-08-21 Thread Florian Eckert

Add device tree supoort for this driver.
Set reference voltage of ADC with the regulator device tree property.
If not set use default 330uV (3.3V).

- vref-supply

Signed-off-by: Florian Eckert 
---
v2:
- use regulator voltage binding
- use dev_dbg
 drivers/hwmon/adcxx.c | 62 +--
 1 file changed, 55 insertions(+), 7 deletions(-)

diff --git a/drivers/hwmon/adcxx.c b/drivers/hwmon/adcxx.c
index 69e0bb97e597..6f3e7d65b5b8 100644
--- a/drivers/hwmon/adcxx.c
+++ b/drivers/hwmon/adcxx.c
@@ -4,6 +4,7 @@
  * The adcxx4s is an AD converter family from National Semiconductor (NS).
  *
  * Copyright (c) 2008 Marc Pignat 
+ * Copyright (c) 2017 Florian Eckert 
  *
  * The adcxx4s communicates with a host processor via an SPI/Microwire Bus
  * interface. This driver supports the whole family of devices with name
@@ -46,9 +47,16 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #define DRVNAME"adcxx"
 
+#define ADCXX1S  1
+#define ADCXX2S  2
+#define ADCXX4S  4
+#define ADCXX8S  8
+
 struct adcxx {
struct device *hwmon_dev;
struct mutex lock;
@@ -159,21 +167,60 @@ static struct sensor_device_attribute ad_input[] = {
SENSOR_ATTR(in7_input, S_IRUGO, adcxx_read, NULL, 7),
 };
 
+#ifdef CONFIG_OF
+static const struct of_device_id adcxx_of_ids[] = {
+   {
+   .compatible = "national,adcxx1s",
+   .data = (void *) ADCXX1S,
+   },
+   {
+   .compatible = "national,adcxx2s",
+   .data = (void *) ADCXX2S,
+   },
+   {
+   .compatible = "national,adcxx4s",
+   .data = (void *) ADCXX4S,
+   },
+   {
+   .compatible = "national,adcxx8s",
+   .   data = (void *) ADCXX8S,
+   },
+   {},
+};
+MODULE_DEVICE_TABLE(of, adcxx_of_ids);
+#endif
+
 /*--*/
 
 static int adcxx_probe(struct spi_device *spi)
 {
-   int channels = spi_get_device_id(spi)->driver_data;
+   const struct of_device_id *match;
+   struct regulator *vref;
+   int vref_uv;
+   int channels;
struct adcxx *adc;
int status;
int i;
 
+   match = of_match_device(adcxx_of_ids, >dev);
+   if (match)
+   channels = (int)(uintptr_t)match->data;
+   else
+   channels = spi_get_device_id(spi)->driver_data;
+
adc = devm_kzalloc(>dev, sizeof(*adc), GFP_KERNEL);
if (!adc)
return -ENOMEM;
 
-   /* set a default value for the reference */
-   adc->reference = 3300;
+   vref = devm_regulator_get_optional(>dev, "vref");
+   if (!IS_ERR(vref)) {
+   vref_uv = regulator_get_voltage(vref);
+   adc->reference = DIV_ROUND_CLOSEST(vref_uv, 1000);
+   }
+   if (!adc->reference)
+   adc->reference = 3300;
+   dev_dbg(>dev, "Reference voltage set to %dmV\n", adc->reference);
+
adc->channels = channels;
mutex_init(>lock);
 
@@ -223,10 +270,10 @@ static int adcxx_remove(struct spi_device *spi)
 }
 
 static const struct spi_device_id adcxx_ids[] = {
-   { "adcxx1s", 1 },
-   { "adcxx2s", 2 },
-   { "adcxx4s", 4 },
-   { "adcxx8s", 8 },
+   { "adcxx1s", ADCXX1S },
+   { "adcxx2s", ADCXX2S },
+   { "adcxx4s", ADCXX4S },
+   { "adcxx8s", ADCXX8S },
{ },
 };
 MODULE_DEVICE_TABLE(spi, adcxx_ids);
@@ -234,6 +281,7 @@ MODULE_DEVICE_TABLE(spi, adcxx_ids);
 static struct spi_driver adcxx_driver = {
.driver = {
.name   = "adcxx",
+   .of_match_table = of_match_ptr(adcxx_of_ids),
},
.id_table = adcxx_ids,
.probe  = adcxx_probe,
-- 
2.11.0

[PATCH v2 1/2] hwmon: (adcxx) add devictree bindings documentation

2017-08-21 Thread Florian Eckert

Document the devicetree bindings for the adcxx.

Signed-off-by: Florian Eckert <f...@dev.tdt.de>
---
v2:
- use regulator voltage binding

 Documentation/devicetree/bindings/hwmon/adcxx.txt | 24 +++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/adcxx.txt

diff --git a/Documentation/devicetree/bindings/hwmon/adcxx.txt 
b/Documentation/devicetree/bindings/hwmon/adcxx.txt
new file mode 100644
index ..a94a5fe21b6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/adcxx.txt
@@ -0,0 +1,24 @@
+adcxx properties
+
+Required properties:
+- compatible: Must be one of the following:
+   - "national,adcxx1s" for adcxx1s
+   - "national,adcxx2s" for adcxx2s
+   - "national,adcxx4s" for adcxx4s
+   - "national,adcxx8s" for adcxx8s
+- reg: SPI address for chip
+
+Optional properties:
+
+- vref-supply
+  The external reference in microvolt for this device is set to this value.
+  If it does not exists the reference will be set to 330uV (3.3V).
+
+Example:
+
+adc@6 {
+   compatible = "national,adcxx2s";
+   reg = <6 0>;
+   spi-max-frequency = <100>;
+   vref-supply = <>;
+};
-- 
2.11.0

[PATCH v2 1/2] hwmon: (adcxx) add devictree bindings documentation

2017-08-21 Thread Florian Eckert

Document the devicetree bindings for the adcxx.

Signed-off-by: Florian Eckert 
---
v2:
- use regulator voltage binding

 Documentation/devicetree/bindings/hwmon/adcxx.txt | 24 +++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/adcxx.txt

diff --git a/Documentation/devicetree/bindings/hwmon/adcxx.txt 
b/Documentation/devicetree/bindings/hwmon/adcxx.txt
new file mode 100644
index ..a94a5fe21b6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/adcxx.txt
@@ -0,0 +1,24 @@
+adcxx properties
+
+Required properties:
+- compatible: Must be one of the following:
+   - "national,adcxx1s" for adcxx1s
+   - "national,adcxx2s" for adcxx2s
+   - "national,adcxx4s" for adcxx4s
+   - "national,adcxx8s" for adcxx8s
+- reg: SPI address for chip
+
+Optional properties:
+
+- vref-supply
+  The external reference in microvolt for this device is set to this value.
+  If it does not exists the reference will be set to 330uV (3.3V).
+
+Example:
+
+adc@6 {
+   compatible = "national,adcxx2s";
+   reg = <6 0>;
+   spi-max-frequency = <100>;
+   vref-supply = <>;
+};
-- 
2.11.0

[PATCH 1/2] hwmon: (ltq-cputemp) add cpu temp sensor for xrx200

2017-08-17 Thread Florian Eckert

Add the lantiq cpu temperature sensor support for xrx200.

Signed-off-by: Florian Eckert <f...@dev.tdt.de>
---
 drivers/hwmon/Kconfig   |   8 +++
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/ltq-cputemp.c | 155 
 3 files changed, 164 insertions(+)
 create mode 100644 drivers/hwmon/ltq-cputemp.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 5ef2814345ef..ed3f5e1d10cc 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -790,6 +790,14 @@ config SENSORS_LTC4261
  This driver can also be built as a module. If so, the module will
  be called ltc4261.
 
+config SENSORS_LTQ_CPUTEMP
+   bool "Lantiq cpu temperature sensor for xrx200"
+   depends on LANTIQ
+   default n
+   help
+ If you say yes here you get support for the temperature
+ sensor inside your xrx200 CPU.
+
 config SENSORS_MAX
tristate "Maxim MAX Serial 8-bit ADC chip and compatibles"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index d4641a9f16c1..c84d9784be98 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_SENSORS_LTC4222)   += ltc4222.o
 obj-$(CONFIG_SENSORS_LTC4245)  += ltc4245.o
 obj-$(CONFIG_SENSORS_LTC4260)  += ltc4260.o
 obj-$(CONFIG_SENSORS_LTC4261)  += ltc4261.o
+obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o
 obj-$(CONFIG_SENSORS_MAX)  += max.o
 obj-$(CONFIG_SENSORS_MAX16065) += max16065.o
 obj-$(CONFIG_SENSORS_MAX1619)  += max1619.o
diff --git a/drivers/hwmon/ltq-cputemp.c b/drivers/hwmon/ltq-cputemp.c
new file mode 100644
index ..a6f820533164
--- /dev/null
+++ b/drivers/hwmon/ltq-cputemp.c
@@ -0,0 +1,155 @@
+/* Lantiq cpu temperature sensor driver for xrx200
+ *
+ * Copyright (C) 2017 Florian Eckert <f...@dev.tdt.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/* gphy1 configuration register contains cpu temperature */
+#define CGU_GPHY1_CR   0x0040
+#define CGU_TEMP_PDBIT(19)
+
+static void ltq_cputemp_enable(void)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR);
+
+   /* wait a short moment to let the SoC get the first temperatur value */
+   mdelay(100);
+}
+
+static void ltq_cputemp_disable(void)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static int ltq_cputemp_read(void)
+{
+   int value;
+
+   /* get the temperature including one decimal place */
+   value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF;
+   value = (value << 2) + value;
+
+   /* range -38 to +154 °C, register value zero is -38.0 °C */
+   value -= 380;
+
+   return value;
+}
+
+static ssize_t show_cputemp(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   int value;
+
+   value = ltq_cputemp_read();
+   /* scale temp to millidegree */
+   value = value * 100;
+
+   return sprintf(buf, "%d\n", value);
+}
+
+static DEVICE_ATTR(temp1_input, S_IRUGO, show_cputemp, NULL);
+
+static struct attribute *ltq_cputemp_attrs[] = {
+   _attr_temp1_input.attr,
+   NULL
+};
+
+ATTRIBUTE_GROUPS(ltq_cputemp);
+
+static int ltq_cputemp_probe(struct platform_device *pdev)
+{
+   int value = 0;
+   int ret;
+   struct device *hwmon_dev;
+
+   /* available on vr9 v1.2 SoCs only */
+   if (ltq_soc_type() != SOC_TYPE_VR9_2)
+   return -ENODEV;
+
+   hwmon_dev = devm_hwmon_device_register_with_groups(>dev,
+   "CPU0",
+   NULL,
+   ltq_cputemp_groups);
+
+   if (IS_ERR(hwmon_dev)) {
+   dev_err(>dev, "Failed to register as hwmon device");
+   ret = PTR_ERR(hwmon_dev);
+   goto error_hwmon;
+   }
+
+   ltq_cputemp_enable();
+   value = ltq_cputemp_read();
+   dev_info(>dev,
+   "Current CPU die temperature: %d.%d °C",
+   value / 10,
+   value

[PATCH 1/2] hwmon: (ltq-cputemp) add cpu temp sensor for xrx200

2017-08-17 Thread Florian Eckert

Add the lantiq cpu temperature sensor support for xrx200.

Signed-off-by: Florian Eckert 
---
 drivers/hwmon/Kconfig   |   8 +++
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/ltq-cputemp.c | 155 
 3 files changed, 164 insertions(+)
 create mode 100644 drivers/hwmon/ltq-cputemp.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 5ef2814345ef..ed3f5e1d10cc 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -790,6 +790,14 @@ config SENSORS_LTC4261
  This driver can also be built as a module. If so, the module will
  be called ltc4261.
 
+config SENSORS_LTQ_CPUTEMP
+   bool "Lantiq cpu temperature sensor for xrx200"
+   depends on LANTIQ
+   default n
+   help
+ If you say yes here you get support for the temperature
+ sensor inside your xrx200 CPU.
+
 config SENSORS_MAX
tristate "Maxim MAX Serial 8-bit ADC chip and compatibles"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index d4641a9f16c1..c84d9784be98 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_SENSORS_LTC4222)   += ltc4222.o
 obj-$(CONFIG_SENSORS_LTC4245)  += ltc4245.o
 obj-$(CONFIG_SENSORS_LTC4260)  += ltc4260.o
 obj-$(CONFIG_SENSORS_LTC4261)  += ltc4261.o
+obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o
 obj-$(CONFIG_SENSORS_MAX)  += max.o
 obj-$(CONFIG_SENSORS_MAX16065) += max16065.o
 obj-$(CONFIG_SENSORS_MAX1619)  += max1619.o
diff --git a/drivers/hwmon/ltq-cputemp.c b/drivers/hwmon/ltq-cputemp.c
new file mode 100644
index ..a6f820533164
--- /dev/null
+++ b/drivers/hwmon/ltq-cputemp.c
@@ -0,0 +1,155 @@
+/* Lantiq cpu temperature sensor driver for xrx200
+ *
+ * Copyright (C) 2017 Florian Eckert 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/* gphy1 configuration register contains cpu temperature */
+#define CGU_GPHY1_CR   0x0040
+#define CGU_TEMP_PDBIT(19)
+
+static void ltq_cputemp_enable(void)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR);
+
+   /* wait a short moment to let the SoC get the first temperatur value */
+   mdelay(100);
+}
+
+static void ltq_cputemp_disable(void)
+{
+   ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static int ltq_cputemp_read(void)
+{
+   int value;
+
+   /* get the temperature including one decimal place */
+   value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF;
+   value = (value << 2) + value;
+
+   /* range -38 to +154 °C, register value zero is -38.0 °C */
+   value -= 380;
+
+   return value;
+}
+
+static ssize_t show_cputemp(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   int value;
+
+   value = ltq_cputemp_read();
+   /* scale temp to millidegree */
+   value = value * 100;
+
+   return sprintf(buf, "%d\n", value);
+}
+
+static DEVICE_ATTR(temp1_input, S_IRUGO, show_cputemp, NULL);
+
+static struct attribute *ltq_cputemp_attrs[] = {
+   _attr_temp1_input.attr,
+   NULL
+};
+
+ATTRIBUTE_GROUPS(ltq_cputemp);
+
+static int ltq_cputemp_probe(struct platform_device *pdev)
+{
+   int value = 0;
+   int ret;
+   struct device *hwmon_dev;
+
+   /* available on vr9 v1.2 SoCs only */
+   if (ltq_soc_type() != SOC_TYPE_VR9_2)
+   return -ENODEV;
+
+   hwmon_dev = devm_hwmon_device_register_with_groups(>dev,
+   "CPU0",
+   NULL,
+   ltq_cputemp_groups);
+
+   if (IS_ERR(hwmon_dev)) {
+   dev_err(>dev, "Failed to register as hwmon device");
+   ret = PTR_ERR(hwmon_dev);
+   goto error_hwmon;
+   }
+
+   ltq_cputemp_enable();
+   value = ltq_cputemp_read();
+   dev_info(>dev,
+   "Current CPU die temperature: %d.%d °C",
+   value / 10,
+   value % 10);
+
+   return 0;
+
+err

[PATCH 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-08-17 Thread Florian Eckert

Document the devicetree bindings for the ltq-cputemp

Signed-off-by: Florian Eckert <f...@dev.tdt.de>
---
 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt | 10 ++
 1 file changed, 10 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt

diff --git a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt 
b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
new file mode 100644
index ..f434aebd3897
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
@@ -0,0 +1,10 @@
+Lantiq cpu temperatur sensor for xrx200
+
+Requires node properties:
+- "compatible" value :
+   "lantiq,cputemp"
+
+Example:
+   cputemp@0 {
+   compatible = "lantiq,cputemp";
+   };
-- 
2.11.0

[PATCH 2/2] hwmon: (ltq-cputemp) add devicetree bindings documentation

2017-08-17 Thread Florian Eckert

Document the devicetree bindings for the ltq-cputemp

Signed-off-by: Florian Eckert 
---
 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt | 10 ++
 1 file changed, 10 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt

diff --git a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt 
b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
new file mode 100644
index ..f434aebd3897
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt
@@ -0,0 +1,10 @@
+Lantiq cpu temperatur sensor for xrx200
+
+Requires node properties:
+- "compatible" value :
+   "lantiq,cputemp"
+
+Example:
+   cputemp@0 {
+   compatible = "lantiq,cputemp";
+   };
-- 
2.11.0

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