[U-Boot] [PATCH v2 3/4] mtd: nand: omap: optimize chip-ecc.calculate() for H/W ECC schemes
chip-ecc.calculate() is used for calculating and fetching of ECC syndrome by
processing the data passed during Read/Write accesses.
All H/W based ECC schemes use GPMC controller to calculate ECC syndrome.
But each BCHx_ECC scheme has its own implemetation of post-processing and
fetching ECC syndrome from GPMC controller.
This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way:
- merges various sub-functions into single omap_calculate_ecc_bch().
- removes omap_ecc_disable() and instead uses it as inline.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap_gpmc.c | 81 ++--
1 file changed, 18 insertions(+), 63 deletions(-)
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index b8f0e86..fa3a82a 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -277,35 +277,28 @@ static void omap_enable_hwecc(struct mtd_info *mtd,
int32_t mode)
writel(ecc_config_val | 0x1, gpmc_cfg-ecc_config);
}
-/*
- * omap_ecc_disable - Disable H/W ECC calculation
- *
- * @mtd: MTD device structure
- */
-static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd)
-{
- writel((readl(gpmc_cfg-ecc_config) ~0x1), gpmc_cfg-ecc_config);
-}
-
/*
* BCH support using ELM module
*/
#if defined(CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW)
/*
- * omap_read_bch8_result - Read BCH result for BCH8 level
- *
- * @mtd: MTD device structure
- * @big_endian:When set read register 3 first
- * @ecc_code: Read syndrome from BCH result registers
+ * omap_calculate_ecc_bch - Read BCH ECC result
+ * @mtd: MTD structure
+ * @dat: unused
+ * @ecc_code: ecc_code buffer
*/
-static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
+static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
uint8_t *ecc_code)
{
+ struct nand_chip *chip = mtd-priv;
+ struct nand_bch_priv *bch = chip-priv;
+ int8_t ret = 0;
uint32_t *ptr;
int8_t i = 0, j;
- if (big_endian) {
+ switch (bch-type) {
+ case ECC_BCH8:
ptr = gpmc_cfg-bch_result_0_3[0].bch_result_x[3];
ecc_code[i++] = readl(ptr) 0xFF;
ptr--;
@@ -316,18 +309,13 @@ static void omap_read_bch8_result(struct mtd_info *mtd,
uint8_t big_endian,
ecc_code[i++] = readl(ptr) 0xFF;
ptr--;
}
- } else {
- ptr = gpmc_cfg-bch_result_0_3[0].bch_result_x[0];
- for (j = 0; j 3; j++) {
- ecc_code[i++] = readl(ptr) 0xFF;
- ecc_code[i++] = (readl(ptr) 8) 0xFF;
- ecc_code[i++] = (readl(ptr) 16) 0xFF;
- ecc_code[i++] = (readl(ptr) 24) 0xFF;
- ptr++;
- }
- ecc_code[i++] = readl(ptr) 0xFF;
- ecc_code[i++] = 0; /* 14th byte is always zero */
+ break;
+ default:
+ ret = -1;
}
+ /* clear result and disable engine */
+ writel((readl(gpmc_cfg-ecc_config) ~0x1), gpmc_cfg-ecc_config);
+ return ret;
}
/*
@@ -366,35 +354,6 @@ static void omap_rotate_ecc_bch(struct mtd_info *mtd,
uint8_t *calc_ecc,
}
/*
- * omap_calculate_ecc_bch - Read BCH ECC result
- *
- * @mtd: MTD structure
- * @dat: unused
- * @ecc_code: ecc_code buffer
- */
-static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
- uint8_t *ecc_code)
-{
- struct nand_chip *chip = mtd-priv;
- struct nand_bch_priv *bch = chip-priv;
- uint8_t big_endian = 1;
- int8_t ret = 0;
-
- if (bch-type == ECC_BCH8)
- omap_read_bch8_result(mtd, big_endian, ecc_code);
- else /* BCH4 and BCH16 currently not supported */
- ret = -1;
-
- /*
-* Stop reading anymore ECC vals and clear old results
-* enable will be called if more reads are required
-*/
- omap_ecc_disable(mtd);
-
- return ret;
-}
-
-/*
* omap_fix_errors_bch - Correct bch error in the data
*
* @mtd: MTD device structure
@@ -592,12 +551,8 @@ static int omap_calculate_ecc_bch(struct mtd_info *mtd,
const uint8_t *dat,
*ecc++ = 0x24 ^ ((val1 8) 0xFF);
*ecc++ = 0xb5 ^ (val1 0xFF);
}
-
- /*
-* Stop reading anymore ECC vals and clear old results
-* enable will be called if more reads are required
-*/
- omap_ecc_disable(mtd);
+ /* Stop reading anymore ECC vals and clear old results */
+ writel((readl(gpmc_cfg-ecc_config) ~0x1), gpmc_cfg-ecc_config);
return ret;
}
--
1.8.1
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/4] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform
BCH8_ECC scheme implemented in omap_gpmc.c driver has following two favours
+---+-+-+
|ECC Scheme | ECC Calculation | Error Detection |
+---+-+-+
|OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine |
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library |
+---+-+-+
Current implementation enables of BCH8_CODE_HW only for AM33xx SoC family.
(using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have
ELM hardware module, and can support ECC error detection using ELM.
This patch
- replaces CONFIG_AM33xx define with
CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW
so that all device families having required h/w capability can use ELM for
error detection in ECC_BCHx schemes.
- replaces CONFIG_NAND_OMAP_BCH8 with
CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW CONFIG_BCH
and separates out code for above mentioned BCH8_ECC implementations so that
driver can be build independently using anyone of them.
CONFIG_BCH is used to enable software BCH library in lib/bch.c
Signed-off-by: Pekon Gupta pe...@ti.com
---
doc/README.nand | 20 +++
drivers/mtd/nand/omap_gpmc.c | 128 ---
include/configs/am335x_evm.h | 1 +
include/configs/ti814x_evm.h | 2 +-
include/configs/tricorder.h | 2 +-
5 files changed, 96 insertions(+), 57 deletions(-)
diff --git a/doc/README.nand b/doc/README.nand
index 913e9b5..b84fce7 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -169,6 +169,26 @@ Configuration Options:
Please convert your driver even if you don't need the extra
flexibility, so that one day we can eliminate the old mechanism.
+ CONFIG_BCH
+ Enables software based BCH ECC algorithm present in lib/bch.c
+ This is used by SoC platforms which do not have in-build hardware
+ engine to calculate and correct BCH ECC.
+
+
+Platform specific configs
+ CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW
+ Enables 8-bit BCH ECC scheme on NAND with following attributes
+ - ECC calculation done by GPMC hardware engine
+ - ECC error detection done by ELM hardware engine
+ - ECC layout compatible with ROM code
+
+ CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+ - ECC calculation done by GPMC hardware engine
+ - ECC error detection done using /lib/bch.c software library
+ - ECC layout is comapatible to SW ECC scheme
+ * requires CONFIG_BCH for enabling lib/bch.c
+
+
NOTE:
=
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index ec1787f..d9a4a5e 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -15,9 +15,7 @@
#include linux/bch.h
#include linux/compiler.h
#include nand.h
-#ifdef CONFIG_AM33XX
#include asm/arch/elm.h
-#endif
static uint8_t cs;
static __maybe_unused struct nand_ecclayout hw_nand_oob =
@@ -274,7 +272,7 @@ static void omap_hwecc_init_bch(struct nand_chip *chip,
int32_t mode)
{
uint32_t val;
uint32_t dev_width = (chip-options NAND_BUSWIDTH_16) 1;
-#ifdef CONFIG_AM33XX
+#if defined(CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW)
uint32_t unused_length = 0;
#endif
uint32_t wr_mode = BCH_WRAPMODE_6;
@@ -283,7 +281,7 @@ static void omap_hwecc_init_bch(struct nand_chip *chip,
int32_t mode)
/* Clear the ecc result registers, select ecc reg as 1 */
writel(ECCCLEAR | ECCRESULTREG1, gpmc_cfg-ecc_control);
-#ifdef CONFIG_AM33XX
+#if defined(CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW)
wr_mode = BCH_WRAPMODE_1;
switch (bch-nibbles) {
@@ -375,10 +373,11 @@ static void __maybe_unused omap_ecc_disable(struct
mtd_info *mtd)
writel((readl(gpmc_cfg-ecc_config) ~0x1), gpmc_cfg-ecc_config);
}
+
/*
- * BCH8 support (needs ELM and thus AM33xx-only)
+ * BCH support using ELM module
*/
-#ifdef CONFIG_AM33XX
+#if defined(CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW)
/*
* omap_read_bch8_result - Read BCH result for BCH8 level
*
@@ -631,12 +630,13 @@ static int omap_read_page_bch(struct mtd_info *mtd,
struct nand_chip *chip,
}
return 0;
}
-#endif /* CONFIG_AM33XX */
+#endif /* CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW */
/*
* OMAP3 BCH8 support (with BCH library)
*/
-#ifdef CONFIG_NAND_OMAP_BCH8
+#if defined(CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) \
+ defined(CONFIG_BCH)
/*
* omap_calculate_ecc_bch - Read BCH ECC result
*
@@ -752,7 +752,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info
*mtd)
chip_priv-control = NULL;
}
}
-#endif /* CONFIG_NAND_OMAP_BCH8 */
+#endif /* CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW CONFIG_BCH */
#ifndef CONFIG_SPL_BUILD
/*
@@ -803,25 +803,43 @@ void omap_nand_switch_ecc(uint32_t hardware, uint32_t
[U-Boot] [PATCH v2 2/4] mtd: nand: omap: optimize chip-ecc.hwctl() for H/W ECC schemes
chip-ecc.hwctl() is used for preparing the H/W controller before read/write
NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.)
Though all ECC schemes in OMAP NAND driver use GPMC controller for generating
ECC syndrome (for both Read/Write accesses). But but in current code
HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this.
This patch
(1) removes omap_hwecc_init() and omap_hwecc_init_bch()
as chip-ecc.hwctl will re-initializeGPMC before every read/write call.
omap_hwecc_init_bch() - omap_enable_ecc_bch()
(2) merges the GPMC configuration code for all ECC schemes into
single omap_enable_hwecc(), thus adding scalability for future ECC schemes.
omap_enable_hwecc() + omap_enable_ecc_bch() - omap_enable_hwecc()
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap_gpmc.c | 207 ---
1 file changed, 58 insertions(+), 149 deletions(-)
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index d9a4a5e..b8f0e86 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -17,6 +17,9 @@
#include nand.h
#include asm/arch/elm.h
+
+#define SECTOR_BYTES 512
+
static uint8_t cs;
static __maybe_unused struct nand_ecclayout hw_nand_oob =
GPMC_NAND_HW_ECC_LAYOUT;
@@ -60,21 +63,6 @@ int omap_spl_dev_ready(struct mtd_info *mtd)
}
#endif
-/*
- * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
- * GPMC controller
- * @mtd:MTD device structure
- *
- */
-static void __maybe_unused omap_hwecc_init(struct nand_chip *chip)
-{
- /*
-* Init ECC Control Register
-* Clear all ECC | Enable Reg1
-*/
- writel(ECCCLEAR | ECCRESULTREG1, gpmc_cfg-ecc_control);
- writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, gpmc_cfg-ecc_size_config);
-}
/*
* gen_true_ecc - This function will generate true ECC value, which
@@ -192,38 +180,6 @@ static int __maybe_unused omap_calculate_ecc(struct
mtd_info *mtd,
}
/*
- * omap_enable_ecc - This function enables the hardware ecc functionality
- * @mtd:MTD device structure
- * @mode: Read/Write mode
- */
-static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t
mode)
-{
- struct nand_chip *chip = mtd-priv;
- uint32_t val, dev_width = (chip-options NAND_BUSWIDTH_16) 1;
-
- switch (mode) {
- case NAND_ECC_READ:
- case NAND_ECC_WRITE:
- /* Clear the ecc result registers, select ecc reg as 1 */
- writel(ECCCLEAR | ECCRESULTREG1, gpmc_cfg-ecc_control);
-
- /*
-* Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
-* tell all regs to generate size0 sized regs
-* we just have a single ECC engine for all CS
-*/
- writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
- gpmc_cfg-ecc_size_config);
- val = (dev_width 7) | (cs 1) | (0x1);
- writel(val, gpmc_cfg-ecc_config);
- break;
- default:
- printf(Error: Unrecognized Mode[%d]!\n, mode);
- break;
- }
-}
-
-/*
* Generic BCH interface
*/
struct nand_bch_priv {
@@ -262,105 +218,63 @@ static __maybe_unused struct nand_bch_priv bch_priv = {
};
/*
- * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
- * GPMC controller
+ * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
* @mtd: MTD device structure
* @mode: Read/Write mode
*/
__maybe_unused
-static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
+static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
{
- uint32_t val;
- uint32_t dev_width = (chip-options NAND_BUSWIDTH_16) 1;
-#if defined(CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW)
- uint32_t unused_length = 0;
-#endif
- uint32_t wr_mode = BCH_WRAPMODE_6;
- struct nand_bch_priv *bch = chip-priv;
-
- /* Clear the ecc result registers, select ecc reg as 1 */
- writel(ECCCLEAR | ECCRESULTREG1, gpmc_cfg-ecc_control);
-
-#if defined(CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW)
- wr_mode = BCH_WRAPMODE_1;
-
- switch (bch-nibbles) {
- case ECC_BCH4_NIBBLES:
- unused_length = 3;
- break;
- case ECC_BCH8_NIBBLES:
- unused_length = 2;
- break;
- case ECC_BCH16_NIBBLES:
- unused_length = 0;
- break;
- }
-
- /*
-* This is ecc_size_config for ELM mode.
-* Here we are using different settings for read and write access and
-* also depending on BCH strength.
-*/
- switch (mode) {
- case NAND_ECC_WRITE:
- /* write access only setup eccsize1 config */
- val = ((unused_length + bch-nibbles) 22);
- break;
-
-
[U-Boot] [PATCH v2 0/4] mtd: nand: omap: optimize and clean-up of OMAP NAND driver
[changes in v2] - added documentation for CONFIG_NAND_OMAP_xx in doc/README.nand - added CONFIG_BCH along with CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW to include software library lib/bch.c - fixed board_nand_init() and omap_enable_hwecc() [Original v1] This patch series updates BCH8_ECC schemes in mtd/nand/omap_gpmc.c driver - adds scalability for higher ECC schemes in future. - removes CONFIG_AM335x and it makes it generic for all platforms. - optimizes read_data paths This series is tested for H/W BCH8_ECC scheme on - AM335x_EVM and TI814x_EVM Pekon Gupta (4): [PATCH 1/4] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform [PATCH 2/4] mtd: nand: omap: optimize chip-ecc.hwctl() for H/W ECC schemes [PATCH 3/4] mtd: nand: omap: optimize chip-ecc.calculate() for H/W ECC schemes [PATCH 4/4] mtd: nand: omap: optimized chip-ecc.correct() for H/W ECC schemes doc/README.nand | 20 ++ drivers/mtd/nand/omap_gpmc.c | 514 +++ include/configs/am335x_evm.h | 1 + include/configs/ti814x_evm.h | 2 +- include/configs/tricorder.h | 2 +- 5 files changed, 203 insertions(+), 336 deletions(-) -- 1.8.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] mtd: nand: omap: optimized chip-ecc.correct() for H/W ECC schemes
chip-ecc.correct() is used for detecting and correcting bit-flips during read
operations. In omap-nand driver it implemented as:
(a) omap_correct_data(): for h/w based ECC_HAM1 scheme
(b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
for ECC_BCH8 scheme using GPMC and software lib/bch.c
(c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW
for ECC_BCH8 scheme using GPMC and ELM
This patch updates (c)
- checks for calc_ecc[]==0x00 so that error_correction is not required for
known good pages.
- adds scalability for other ECC_BCHx scheme by merging following
omap_rotate_ecc_bch() + omap_fix_errors_bch() = omap_correct_data_bch()
- fixing logic for bit-flip correction based on error_loc[count]
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap_gpmc.c | 124 +++
1 file changed, 44 insertions(+), 80 deletions(-)
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index fa3a82a..8c2ba53 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -19,6 +19,8 @@
#define SECTOR_BYTES 512
+/* 4 bit padding to make byte aligned, 56 = 52 + 4 */
+#define BCH4_BIT_PAD 4
static uint8_t cs;
static __maybe_unused struct nand_ecclayout hw_nand_oob =
@@ -319,77 +321,6 @@ static int omap_calculate_ecc_bch(struct mtd_info *mtd,
const uint8_t *dat,
}
/*
- * omap_rotate_ecc_bch - Rotate the syndrome bytes
- *
- * @mtd: MTD device structure
- * @calc_ecc: ECC read from ECC registers
- * @syndrome: Rotated syndrome will be retuned in this array
- *
- */
-static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
- uint8_t *syndrome)
-{
- struct nand_chip *chip = mtd-priv;
- struct nand_bch_priv *bch = chip-priv;
- uint8_t n_bytes = 0;
- int8_t i, j;
-
- switch (bch-type) {
- case ECC_BCH4:
- n_bytes = 8;
- break;
-
- case ECC_BCH16:
- n_bytes = 28;
- break;
-
- case ECC_BCH8:
- default:
- n_bytes = 13;
- break;
- }
-
- for (i = 0, j = (n_bytes-1); i n_bytes; i++, j--)
- syndrome[i] = calc_ecc[j];
-}
-
-/*
- * omap_fix_errors_bch - Correct bch error in the data
- *
- * @mtd: MTD device structure
- * @data: Data read from flash
- * @error_count:Number of errors in data
- * @error_loc: Locations of errors in the data
- *
- */
-static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
- uint32_t error_count, uint32_t *error_loc)
-{
- struct nand_chip *chip = mtd-priv;
- struct nand_bch_priv *bch = chip-priv;
- uint8_t count = 0;
- uint32_t error_byte_pos;
- uint32_t error_bit_mask;
- uint32_t last_bit = (bch-nibbles * 4) - 1;
-
- /* Flip all bits as specified by the error location array. */
- /* FOR( each found error location flip the bit ) */
- for (count = 0; count error_count; count++) {
- if (error_loc[count] last_bit) {
- /* Remove the ECC spare bits from correction. */
- error_loc[count] -= (last_bit + 1);
- /* Offset bit in data region */
- error_byte_pos = ((512 * 8) -
- (error_loc[count]) - 1) / 8;
- /* Error Bit mask */
- error_bit_mask = 0x1 (error_loc[count] % 8);
- /* Toggle the error bit to make the correction. */
- data[error_byte_pos] ^= error_bit_mask;
- }
- }
-}
-
-/*
* omap_correct_data_bch - Compares the ecc read from nand spare area
* with ECC registers values and corrects one bit error if it has occured
*
@@ -405,16 +336,26 @@ static int omap_correct_data_bch(struct mtd_info *mtd,
uint8_t *dat,
{
struct nand_chip *chip = mtd-priv;
struct nand_bch_priv *bch = chip-priv;
+ uint32_t eccbytes = chip-ecc.bytes;
uint8_t syndrome[28];
- uint32_t error_count = 0;
+ uint32_t error_count = 0, error_max;
uint32_t error_loc[8];
- uint32_t i, ecc_flag;
+ uint32_t i, j, ecc_flag = 0;
+ uint8_t count, ret = 0;
+ uint32_t byte_pos, bit_pos;
+
+ /* check calculated ecc */
+ for (i = 0; i chip-ecc.bytes !ecc_flag; i++)
+ if (calc_ecc[i] != 0x00)
+ ecc_flag = 1;
+ if (!ecc_flag)
+ return 0;
+ /* check for whether its a erased-page */
ecc_flag = 0;
- for (i = 0; i chip-ecc.bytes; i++)
+ for (i = 0; i chip-ecc.bytes !ecc_flag; i++)
if (read_ecc[i] != 0xff)
ecc_flag = 1;
-
if (!ecc_flag)
return 0;
@@ -425,20 +366,43 @@ static int omap_correct_data_bch(struct mtd_info
Re: [U-Boot] [PATCH v3 1/4] arm, am33xx: add defines for gmii_sel_register bits
On Monday 12 August 2013 11:06 PM, Mugunthan V N wrote: On Monday 12 August 2013 07:52 PM, Tom Rini wrote: +#define GMII2_SEL_MII0x0 +#define GMII2_SEL_RMII0x4 +#define GMII2_SEL_RGMII 0x8 +#define GMII2_SEL_NOTUSED 0xc NOTUSED not needed as it is not supposed to be used. same here ... I think Not Used in the TRM here means this port is not used rather than this combination of bits is not to be used, so the changes are correct. But having this define is not useful as far as I can think of as there is not abstraction API for this to check what user is passing. But I leave it to Tom's decision to have this change or not. Other than this the patch looks good to me. Acked-by: Mugunthan V N mugunthan...@ti.com I had a discussion with the hardware team internally and the comment is *When these bits are set to 11b the RGMII is selected with internal delay mode which was not timing closed. Therefore this register setting is not supported so it should not be used. The respective pin multiplexing should be used to deselect any unused CPGMAC pins.*c The same will be updated in the TRM soon. So can you remove NOTUSED define and resubmit the patch again and can include my Acked-by in your next version patch. Regards Mugunthan V N ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] SPL: Makefile: Build a separate autoconf.mk for SPL
From: Zhang Ying rock.ap.freescale.net SPL defines CONFIG_SPL_BUILD but this does not percolate to the autoconf.mk Makefile. As a result the build breaks when CONFIG_SPL_BUILD is used in the board-specific include header file. With this, there is a possibility of having a CONFIG option defined in the header file but not defined in the Makefile causing all kinds of build failure and problems. It also messes things for up, for example, when one might want to undefine options to keep the SPL small and doesn't want to be stuck with the CONFIG options used for U-boot. Lastly, this also avoids defining special CONFIG_SPL_ variables for cases where some options are required in U-boot but not in SPL. We add a spl-autoconf.mk rule that is generated for SPL with the CONFIG_SPL_BUILD flag and conditionally include it for SPL builds. Signed-off-by: Zhang Ying rock.ap.freescale.net --- Change from v2: - Fixed the reported build breakage of am335x_evm_usbspl. Change from v1: - Fixed issue where builds in a different directory were failing. Makefile | 19 +-- config.mk| 6 ++ spl/Makefile | 1 + 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index d545d30..75df06a 100644 --- a/Makefile +++ b/Makefile @@ -613,6 +613,7 @@ updater: # Explicitly make _depend in subdirs containing multiple targets to prevent # parallel sub-makes creating .depend files simultaneously. depend dep:$(TIMESTAMP_FILE) $(VERSION_FILE) \ + $(obj)include/spl-autoconf.mk \ $(obj)include/autoconf.mk \ $(obj)include/generated/generic-asm-offsets.h \ $(obj)include/generated/asm-offsets.h @@ -694,12 +695,23 @@ $(obj)include/autoconf.mk: $(obj)include/config.h sed -n -f tools/scripts/define2mk.sed $@.tmp \ mv $@.tmp $@ +# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL) +$(obj)include/spl-autoconf.mk: $(obj)include/config.h + @$(XECHO) Generating $@ ; \ + set -e ; \ + : Extract the config macros ; \ + $(CPP) $(CFLAGS) -DCONFIG_SPL_BUILD -DDO_DEPS_ONLY -dM include/common.h | \ + sed -n -f tools/scripts/define2mk.sed $@.tmp \ + mv $@.tmp $@ + $(obj)include/generated/generic-asm-offsets.h: $(obj)include/autoconf.mk.dep \ + $(obj)include/spl-autoconf.mk \ $(obj)lib/asm-offsets.s @$(XECHO) Generating $@ tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@ $(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \ + $(obj)include/spl-autoconf.mk \ $(src)lib/asm-offsets.c @mkdir -p $(obj)lib $(CC) -DDO_DEPS_ONLY \ @@ -707,11 +719,13 @@ $(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \ -o $@ $(src)lib/asm-offsets.c -c -S $(obj)include/generated/asm-offsets.h: $(obj)include/autoconf.mk.dep \ + $(obj)include/spl-autoconf.mk \ $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s @$(XECHO) Generating $@ tools/scripts/make-asm-offsets $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s $@ -$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s: $(obj)include/autoconf.mk.dep +$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s: $(obj)include/autoconf.mk.dep \ + $(obj)include/spl-autoconf.mk @mkdir -p $(obj)$(CPUDIR)/$(SOC) if [ -f $(src)$(CPUDIR)/$(SOC)/asm-offsets.c ];then \ $(CC) -DDO_DEPS_ONLY \ @@ -783,7 +797,8 @@ include/license.h: tools/bin2header COPYING unconfig: @rm -f $(obj)include/config.h $(obj)include/config.mk \ $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \ - $(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep + $(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep \ + $(obj)include/spl-autoconf.mk %_config:: unconfig @$(MKCONFIG) -A $(@:_config=) diff --git a/config.mk b/config.mk index 3e84f36..54e99f4 100644 --- a/config.mk +++ b/config.mk @@ -145,7 +145,13 @@ CHECK = sparse # # Load generated board configuration +ifeq ($(CONFIG_SPL_BUILD),y) +# Include SPL autoconf +sinclude $(OBJTREE)/include/spl-autoconf.mk +else +# Include normal autoconf sinclude $(OBJTREE)/include/autoconf.mk +endif sinclude $(OBJTREE)/include/config.mk # Some architecture config.mk files need to know what CPUDIR is set to, diff --git a/spl/Makefile b/spl/Makefile index 6e5299b..43db01f 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -80,6 +80,7 @@ LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o +LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/libphy.o LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o LIBS-$(CONFIG_SPL_USBETH_SUPPORT) +=
[U-Boot] [RFC][PATCH v3] ARM: mxs: Added application UART driver
The driver makes it possible to use an application UART as
the U-Boot output console for Freescale i.MX23/i.MX28 devices.
Signed-off-by: Andreas Wass andreas.w...@dalelven.com
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Marek Vasut ma...@denx.de
---
Changes for v2:
- Added comment that regs-uartapp.h is pulled from LTIB
- BM_ prefixes removed and _MASK suffixes added instead
- BP_ prefixes removed and _OFFSET suffixes added instead
- BF_ defines removed altogether
- CONFIG_MXS_AUART_CLK renamed to MXS_AUART_CLK and guarding ifndef removed
- Added comments describing what is set and unset during init of driver
- Added newline that was accidently removed from serial.c
Changes for v3:
- All BV_ values are now on the form (value something)
- BV_ prefix removed and double underscore substituted with a single
- File comment of mxs_auart.c now attributes what the driver is based on
- Uses gd-baudrate instead of CONFIG_BAUDRATE
- If gd-baudrate is 0 it reverts back to CONFIG_BAUDRATE
- Checks the validity of the div value calculated when setting the baudrate
- Magic numbers are now defines instead
- Cleanup of comments
- Cleanup of commit message
arch/arm/include/asm/arch-mxs/regs-uartapp.h | 249 +++
drivers/serial/Makefile | 1 +
drivers/serial/mxs_auart.c | 151
drivers/serial/serial.c | 2 +
4 files changed, 403 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mxs/regs-uartapp.h
create mode 100644 drivers/serial/mxs_auart.c
diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h
b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
new file mode 100644
index 000..1288d18
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
@@ -0,0 +1,249 @@
+/*
+ * Freescale MXS UARTAPP Register Definitions
+ *
+ * Copyright (C) 2013 Andreas Wass andreas.w...@dalelven.com
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM___MXS_UARTAPP_H
+#define __ARCH_ARM___MXS_UARTAPP_H
+
+#include asm/imx-common/regs-common.h
+
+#ifndef __ASSEMBLY__
+struct mxs_uartapp_regs {
+ mxs_reg_32(hw_uartapp_ctrl0)
+ mxs_reg_32(hw_uartapp_ctrl1)
+ mxs_reg_32(hw_uartapp_ctrl2)
+ mxs_reg_32(hw_uartapp_linectrl)
+ mxs_reg_32(hw_uartapp_linectrl2)
+ mxs_reg_32(hw_uartapp_intr)
+ mxs_reg_32(hw_uartapp_data)
+ mxs_reg_32(hw_uartapp_stat)
+ mxs_reg_32(hw_uartapp_debug)
+ mxs_reg_32(hw_uartapp_version)
+ mxs_reg_32(hw_uartapp_autobaud)
+};
+#endif
+
+
+#define UARTAPP_CTRL0_SFTRST_MASK (1 31)
+#define UARTAPP_CTRL0_CLKGATE_MASK (1 30)
+#define UARTAPP_CTRL0_RUN_MASK (1 29)
+#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 28)
+#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 27)
+#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET (1 4)
+#define UARTAPP_CTRL0_RXTIMEOUT_MASK 0x07FF
+#define UARTAPP_CTRL0_XFER_COUNT_OFFSET0
+#define UARTAPP_CTRL0_XFER_COUNT_MASK 0x
+
+#define UARTAPP_CTRL1_RSVD2_OFFSET 29
+#define UARTAPP_CTRL1_RSVD2_MASK 0xE000
+
+#define UARTAPP_CTRL1_RUN_MASK (1 28)
+#define UARTAPP_CTRL1_RSVD1_OFFSET 16
+#define UARTAPP_CTRL1_RSVD1_MASK 0x0FFF
+
+#define UARTAPP_CTRL1_XFER_COUNT_OFFSET0
+#define UARTAPP_CTRL1_XFER_COUNT_MASK 0x
+
+#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 31)
+#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 30)
+#define UARTAPP_CTRL2_INVERT_TX_MASK (1 29)
+#define UARTAPP_CTRL2_INVERT_RX_MASK (1 28)
+#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 27)
+#define UARTAPP_CTRL2_DMAONERR_MASK(1 26)
+#define UARTAPP_CTRL2_TXDMAE_MASK (1 25)
+#define UARTAPP_CTRL2_RXDMAE_MASK (1 24)
+#define UARTAPP_CTRL2_RSVD2_MASK (1 23)
+#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
+#define UARTAPP_CTRL2_RXIFLSEL_MASK0x0070
+
+#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF(0x2 20)
+#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 20)
+#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID5(0x5 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID6
[U-Boot] [U-boot] U-Boot Driver Model question
Hi, experts: I found U-Boot Driver Model introduction ppt at SLM2012 Conference. It seems current drivers in u-boot was still not implemented by this Driver Model? It was just a long-term plan? Best wishes, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC][PATCH v4] ARM: mxs: Added application UART driver
The driver makes it possible to use an application UART as
the U-Boot output console for Freescale i.MX23/i.MX28 devices.
Signed-off-by: Andreas Wass andreas.w...@dalelven.com
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Marek Vasut ma...@denx.de
---
Changes for v2:
- Added comment that regs-uartapp.h is pulled from LTIB
- BM_ prefixes removed and _MASK suffixes added instead
- BP_ prefixes removed and _OFFSET suffixes added instead
- BF_ defines removed altogether
- CONFIG_MXS_AUART_CLK renamed to MXS_AUART_CLK and guarding ifndef removed
- Added comments describing what is set and unset during init of driver
- Added newline that was accidently removed from serial.c
Changes for v3:
- All BV_ values are now on the form (value something)
- BV_ prefix removed and double underscore substituted with a single
- File comment of mxs_auart.c now attributes what the driver is based on
- Uses gd-baudrate instead of CONFIG_BAUDRATE
- If gd-baudrate is 0 it reverts back to CONFIG_BAUDRATE
- Checks the validity of the div value calculated when setting the baudrate
- Magic numbers are now defines instead
- Cleanup of comments
- Cleanup of commit message
Changes for v4:
- Fixed UARTAPP_LINECTRL2_WLEN_*BITS values
drivers/serial/Makefile | 1 +
drivers/serial/mxs_auart.c | 151
drivers/serial/serial.c | 2 +
4 files changed, 403 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mxs/regs-uartapp.h
create mode 100644 drivers/serial/mxs_auart.c
diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h
b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
new file mode 100644
index 000..abd62c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
@@ -0,0 +1,249 @@
+/*
+ * Freescale MXS UARTAPP Register Definitions
+ *
+ * Copyright (C) 2013 Andreas Wass andreas.w...@dalelven.com
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM___MXS_UARTAPP_H
+#define __ARCH_ARM___MXS_UARTAPP_H
+
+#include asm/imx-common/regs-common.h
+
+#ifndef __ASSEMBLY__
+struct mxs_uartapp_regs {
+ mxs_reg_32(hw_uartapp_ctrl0)
+ mxs_reg_32(hw_uartapp_ctrl1)
+ mxs_reg_32(hw_uartapp_ctrl2)
+ mxs_reg_32(hw_uartapp_linectrl)
+ mxs_reg_32(hw_uartapp_linectrl2)
+ mxs_reg_32(hw_uartapp_intr)
+ mxs_reg_32(hw_uartapp_data)
+ mxs_reg_32(hw_uartapp_stat)
+ mxs_reg_32(hw_uartapp_debug)
+ mxs_reg_32(hw_uartapp_version)
+ mxs_reg_32(hw_uartapp_autobaud)
+};
+#endif
+
+
+#define UARTAPP_CTRL0_SFTRST_MASK (1 31)
+#define UARTAPP_CTRL0_CLKGATE_MASK (1 30)
+#define UARTAPP_CTRL0_RUN_MASK (1 29)
+#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 28)
+#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 27)
+#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET (1 4)
+#define UARTAPP_CTRL0_RXTIMEOUT_MASK 0x07FF
+#define UARTAPP_CTRL0_XFER_COUNT_OFFSET0
+#define UARTAPP_CTRL0_XFER_COUNT_MASK 0x
+
+#define UARTAPP_CTRL1_RSVD2_OFFSET 29
+#define UARTAPP_CTRL1_RSVD2_MASK 0xE000
+
+#define UARTAPP_CTRL1_RUN_MASK (1 28)
+#define UARTAPP_CTRL1_RSVD1_OFFSET 16
+#define UARTAPP_CTRL1_RSVD1_MASK 0x0FFF
+
+#define UARTAPP_CTRL1_XFER_COUNT_OFFSET0
+#define UARTAPP_CTRL1_XFER_COUNT_MASK 0x
+
+#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 31)
+#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 30)
+#define UARTAPP_CTRL2_INVERT_TX_MASK (1 29)
+#define UARTAPP_CTRL2_INVERT_RX_MASK (1 28)
+#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 27)
+#define UARTAPP_CTRL2_DMAONERR_MASK(1 26)
+#define UARTAPP_CTRL2_TXDMAE_MASK (1 25)
+#define UARTAPP_CTRL2_RXDMAE_MASK (1 24)
+#define UARTAPP_CTRL2_RSVD2_MASK (1 23)
+#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
+#define UARTAPP_CTRL2_RXIFLSEL_MASK0x0070
+
+#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF(0x2 20)
+#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 20)
+#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID5(0x5 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID6(0x6 20)
[U-Boot] [PATCH] mxc_spi: bugfix for double incrementing read pointer on unaligned buffers in spi_xchg_single
If dout buffer is not 32 bit-aligned or data to transmit is not multiple
of 32 bit the read data pointer is already incremented on single byte reads.
Signed-off-by: Timo Herbrecher t.herbrec...@gateware.de
---
drivers/spi/mxc_spi.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index fd72a65..95dd03f 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -255,8 +255,8 @@ int spi_xchg_single(struct spi_slave *slave,
unsigned int bitlen,
} else {
data = *(u32 *)dout;
data = cpu_to_be32(data);
+ dout += 4;
}
- dout += 4;
}
debug(Sending SPI 0x%x\n, data);
reg_write(regs-txdata, data);
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4] Add Nanobone board support
NanoBone Specification:
---
CPU:
TI AM335x
Memory:
256MB DDR3
64MB NOR flash
256MB NAND flash
128KB FRAM
Ethernet:
2 x 10/100 connected to SMSC LAN8710 PHY
USB:
1 x USB2.0 Type A
I2C:
2Kbit EEPROM (Microchip 24AA02)
RTC (Maxim DS1338)
GPIO Expander (Microchip MCP23017)
Expansion connector:
6 x UART
1 x MMC/SD
1 x USB2.0
Signed-off-by: Mark Jackson m...@newflow.co.uk
---
Changes in v4:
- Tweaked after comments from Tom Rini
- LEDs now initialised
Changes in v3:
- Rebased on TI U-Boot
Changes in v2:
- Tweaked after comments from Tom Rini
MAINTAINERS |4 +
board/newflow/nanobone/Makefile | 38 +
board/newflow/nanobone/board.c| 298 +
board/newflow/nanobone/mux.c | 195
board/newflow/nanobone/u-boot.lds | 98
boards.cfg|2 +
include/configs/nanobone.h| 295
7 files changed, 930 insertions(+)
create mode 100644 board/newflow/nanobone/Makefile
create mode 100644 board/newflow/nanobone/board.c
create mode 100644 board/newflow/nanobone/mux.c
create mode 100644 board/newflow/nanobone/u-boot.lds
create mode 100644 include/configs/nanobone.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 081cf96..4f44e8f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -717,6 +717,10 @@ Ilko Iliev il...@ronetix.at
PM9263 AT91SAM9263
PM9G45 ARM926EJS (AT91SAM9G45 SoC)
+Mark Jackson m...@newflow.co.uk
+
+ NANOBONEARM ARMV7 (AM33xx Soc)
+
Michael Jones michael.jo...@matrix-vision.de
omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
diff --git a/board/newflow/nanobone/Makefile b/board/newflow/nanobone/Makefile
new file mode 100644
index 000..3dbeeda
--- /dev/null
+++ b/board/newflow/nanobone/Makefile
@@ -0,0 +1,38 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
+COBJS := mux.o
+endif
+
+COBJS += board.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/newflow/nanobone/board.c b/board/newflow/nanobone/board.c
new file mode 100644
index 000..743454b
--- /dev/null
+++ b/board/newflow/nanobone/board.c
@@ -0,0 +1,298 @@
+/*
+ * board.c
+ *
+ * Board functions for Newflow NanoBone board
+ *
+ * Copyright (C) 2013, Newflow Ltd - http://www.newflow.co.uk/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include spl.h
+#include asm/arch/cpu.h
+#include asm/arch/hardware.h
+#include asm/arch/omap.h
+#include asm/arch/ddr_defs.h
+#include asm/arch/clock.h
+#include asm/arch/gpio.h
+#include asm/arch/mmc_host_def.h
+#include asm/arch/sys_proto.h
+#include asm/arch/mem.h
+#include asm/io.h
+#include asm/emif.h
+#include asm/gpio.h
+#include i2c.h
+#include miiphy.h
+#include cpsw.h
+#include board.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* NOR Flash config */
+#define NOR_CS 0
+#define NOR_BASE 0x0800
+#define NOR_SIZE GPMC_SIZE_128M
+static u32 gpmc_nor_config[GPMC_MAX_REG] = {
+ 0x1200,
+ 0x00101000,
+ 0x00030301,
+ 0x10041004,
+ 0x010f1010,
+ 0x08070280,
+ 0
+};
+
+/* FRAM config */
+#define FRAM_CS1
+#define FRAM_BASE 0x1c00
+#define FRAM_SIZE GPMC_SIZE_16M
+static u32 gpmc_fram_config[GPMC_MAX_REG] = {
+ 0x1200,
+ 0x00101000,
+ 0x00020201,
+ 0x0f030f03,
+ 0x010d1010,
+ 0x000301c0,
+ 0
+};
+
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+/* MII mode defines */
+#define PORT1_MII_MODE_ENABLE 0x0
+#define PORT2_MII_MODE_ENABLE 0x0
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41J128MJT125_RD_DQS,
+ .datawdsratio0 = MT41J128MJT125_WR_DQS,
+ .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
+ .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41J128MJT125_RATIO,
+ .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
+
[U-Boot] [PATCH v2 1/4] core support of arm64
From: David Feng feng...@phytium.com.cn
This patch provide u-boot with arm64 support. Currently, it works on
Foundation Model for armv8 or Fast Model for armv8.
Signed-off-by: David Feng feng...@phytium.com.cn
---
Changes for v2:
- fix EXPORT_FUNC macro to use register x9 according to Scott Wood mail
- redefine some copyright text
- add declaration of cache related functions, remove some compiler warnnings
common/cmd_bdinfo.c | 32 +
common/fdt_support.c| 66 ++-
common/image.c |5 ++--
doc/README.arm64| 10 +++
examples/standalone/stubs.c | 13 +
include/image.h |1 +
lib/asm-offsets.c |4 ---
7 files changed, 93 insertions(+), 38 deletions(-)
create mode 100644 doc/README.arm64
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index af884b8..4a7b61b 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -517,6 +517,38 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
return 0;
}
+#elif defined(CONFIG_ARM64)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+
+ for (i = 0; i CONFIG_NR_DRAM_BANKS; ++i) {
+ print_num(DRAM bank, i);
+ print_num( - start, gd-bd-bi_dram[i].start);
+ print_num( - size, gd-bd-bi_dram[i].size);
+ }
+
+ printf(baudrate= %ld bps\n, gd-bd-bi_baudrate);
+
+ print_num(relocaddr, gd-relocaddr);
+ print_num(reloc off, gd-reloc_off);
+ print_num(sp start , gd-start_addr_sp);
+#ifndef CONFIG_SYS_DCACHE_OFF
+ print_num(TLB addr, gd-arch.tlb_addr);
+#endif
+
+ printf(CPU frequency = %ld MHz\n, gd-cpu_clk);
+ printf(DDR frequency = %ld MHz\n, gd-mem_clk);
+
+#if defined(CONFIG_CMD_NET)
+ print_eth(0);
+ printf(ip_addr = %s\n, getenv(ipaddr));
+#endif
+
+ return 0;
+}
+
#else
#error a case for this architecture does not exist!
#endif
diff --git a/common/fdt_support.c b/common/fdt_support.c
index b034c98..9bc5821 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -21,6 +21,34 @@
*/
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Get cells len in bytes
+ * if #-cells property is 2 then len is 8
+ * otherwise len is 4
+ */
+static int get_cells_len(void *blob, char *nr_cells_name)
+{
+ const fdt32_t *cell;
+
+ cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
+ if (cell fdt32_to_cpu(*cell) == 2)
+ return 8;
+
+ return 4;
+}
+
+/*
+ * Write a 4 or 8 byte big endian cell
+ */
+static void write_cell(u8 *addr, u64 val, int size)
+{
+ int shift = (size - 1) * 8;
+ while (size-- 0) {
+ *addr++ = (val shift) 0xff;
+ shift -= 8;
+ }
+}
+
/**
* fdt_getprop_u32_default - Find a node and return it's property or a default
*
@@ -131,9 +159,9 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff)
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force)
{
- int nodeoffset;
+ int nodeoffset, addr_cell_len;
int err, j, total;
- fdt32_t tmp;
+ fdt64_t tmp;
const char *path;
uint64_t addr, size;
@@ -170,9 +198,11 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong
initrd_end, int force)
return err;
}
+ addr_cell_len = get_cells_len(fdt, #address-cells);
+
path = fdt_getprop(fdt, nodeoffset, linux,initrd-start, NULL);
if ((path == NULL) || force) {
- tmp = cpu_to_fdt32(initrd_start);
+ write_cell((u8 *)tmp, initrd_start, addr_cell_len);
err = fdt_setprop(fdt, nodeoffset,
linux,initrd-start, tmp, sizeof(tmp));
if (err 0) {
@@ -181,7 +211,7 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong
initrd_end, int force)
fdt_strerror(err));
return err;
}
- tmp = cpu_to_fdt32(initrd_end);
+ write_cell((u8 *)tmp, initrd_end, addr_cell_len);
err = fdt_setprop(fdt, nodeoffset,
linux,initrd-end, tmp, sizeof(tmp));
if (err 0) {
@@ -343,34 +373,6 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
do_fixup_by_compat(fdt, compat, prop, tmp, 4, create);
}
-/*
- * Get cells len in bytes
- * if #-cells property is 2 then len is 8
- * otherwise len is 4
- */
-static int get_cells_len(void *blob, char *nr_cells_name)
-{
- const fdt32_t *cell;
-
- cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
- if (cell fdt32_to_cpu(*cell) == 2)
- return 8;
-
- return 4;
-}
-
-/*
- * Write a 4 or 8 byte big endian cell
- */
-static void write_cell(u8 *addr, u64 val, int size)
-{
- int shift = (size - 1)
[U-Boot] [PATCH v2 3/4] arm64/lib support of arm64
From: David Feng feng...@phytium.com.cn This patch provide u-boot with arm64 support. Currently, it works on Foundation Model for armv8 or Fast Model for armv8. Signed-off-by: David Feng feng...@phytium.com.cn --- Changes for v2: - fix EXPORT_FUNC macro to use register x9 according to Scott Wood mail - redefine some copyright text - add declaration of cache related functions, remove some compiler warnnings arch/arm64/lib/Makefile | 64 ++ arch/arm64/lib/board.c | 456 +++ arch/arm64/lib/bootm.c | 211 arch/arm64/lib/cache.c | 282 ++ arch/arm64/lib/crt0.S | 129 arch/arm64/lib/interrupts.c | 109 +++ arch/arm64/lib/relocate.S | 72 +++ arch/arm64/lib/reset.c | 37 arch/arm64/lib/timer.c | 95 + 9 files changed, 1455 insertions(+) create mode 100644 arch/arm64/lib/Makefile create mode 100644 arch/arm64/lib/board.c create mode 100644 arch/arm64/lib/bootm.c create mode 100644 arch/arm64/lib/cache.c create mode 100644 arch/arm64/lib/crt0.S create mode 100644 arch/arm64/lib/interrupts.c create mode 100644 arch/arm64/lib/relocate.S create mode 100644 arch/arm64/lib/reset.c create mode 100644 arch/arm64/lib/timer.c diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile new file mode 100644 index 000..87fa803 --- /dev/null +++ b/arch/arm64/lib/Makefile @@ -0,0 +1,64 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(ARCH).o +LIBGCC = $(obj)libgcc.o + +COBJS-y+= board.o +COBJS-y+= interrupts.o +COBJS-y+= reset.o +COBJS-y+= cache.o +COBJS-y+= timer.o + +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o + +SOBJS-y += crt0.o +SOBJS-y += relocate.o + +SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \ + $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +LGOBJS := $(addprefix $(obj),$(GLSOBJS)) \ + $(addprefix $(obj),$(GLCOBJS)) + +# Always build libarm64.o +TARGETS:= $(LIB) + +all: $(TARGETS) + +$(LIB):$(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +$(LIBGCC): $(obj).depend $(LGOBJS) + $(call cmd_link_o_target, $(LGOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm64/lib/board.c b/arch/arm64/lib/board.c new file mode 100644 index 000..a8147a5 --- /dev/null +++ b/arch/arm64/lib/board.c @@ -0,0 +1,456 @@ +/* + * (C) Copyright 2013 + * David Feng, Phytium Technology feng...@phytium.com.cn + * + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, w...@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH www.elinos.com + * Marius Groeger mgroe...@sysgo.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include common.h +#include command.h +#include malloc.h +#include stdio_dev.h +#include version.h +#include net.h +#include serial.h +#include nand.h +#include onenand_uboot.h +#include mmc.h +#include libfdt.h +#include fdtdec.h +#include post.h +#include logbuff.h +#include pci.h +#include
[U-Boot] [PATCH v2 2/4] board support of arm64
From: David Feng feng...@phytium.com.cn
This patch provide u-boot with arm64 support. Currently, it works on
Foundation Model for armv8 or Fast Model for armv8.
Signed-off-by: David Feng feng...@phytium.com.cn
---
Changes for v2:
- fix EXPORT_FUNC macro to use register x9 according to Scott Wood mail
- redefine some copyright text
- add declaration of cache related functions, remove some compiler warnnings
board/armltd/dts/vexpress64.dts | 215 ++
board/armltd/vexpress64/Makefile | 43 +++
board/armltd/vexpress64/vexpress64.c | 63 ++
boards.cfg |1 +
include/configs/vexpress_aemv8a.h| 200 +++
5 files changed, 522 insertions(+)
create mode 100644 board/armltd/dts/vexpress64.dts
create mode 100644 board/armltd/vexpress64/Makefile
create mode 100644 board/armltd/vexpress64/vexpress64.c
create mode 100644 include/configs/vexpress_aemv8a.h
diff --git a/board/armltd/dts/vexpress64.dts b/board/armltd/dts/vexpress64.dts
new file mode 100644
index 000..3814e01
--- /dev/null
+++ b/board/armltd/dts/vexpress64.dts
@@ -0,0 +1,215 @@
+/*
+ * ARM Ltd. Fast Models
+ *
+ * Architecture Envelope Model (AEM) ARMv8-A
+ * ARMAEMv8AMPCT
+ *
+ * RTSM_VE_AEMv8A.lisa
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x8000 0x0001;
+
+/ {
+ /* boot configurations for u-boot */
+ config {
+ /*bootdelay = 1;*/
+ kernel-offset = 0x10;
+ rootdisk-offset = 0x80;
+ bootcmd = bootm 0x10 0x80:0x200;
+ };
+};
+
+/ {
+ model = RTSM_VE_AEMv8A;
+ compatible = arm,rtsm_ve,aemv8a, arm,vexpress;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ /* chosen */
+ /* generated by u-boot */
+
+
+ aliases {
+ serial0 = v2m_serial0;
+ serial1 = v2m_serial1;
+ serial2 = v2m_serial2;
+ serial3 = v2m_serial3;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 0;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 1;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 2;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 3;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ };
+
+ memory@8000 {
+ device_type = memory;
+ reg = 0x 0x8000 0 0x8000,
+ 0x0008 0x8000 0 0x8000;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = arm,cortex-a15-gic, arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x0 0x2c001000 0 0x1000,
+ 0x0 0x2c002000 0 0x1000,
+ 0x0 0x2c004000 0 0x2000,
+ 0x0 0x2c006000 0 0x2000;
+ interrupts = 1 9 0xf04;
+ };
+
+ timer {
+ compatible = arm,armv8-timer;
+ interrupts = 1 13 0xff01,
+1 14 0xff01,
+1 11 0xff01,
+1 10 0xff01;
+ clock-frequency = 1;
+ };
+
+ pmu {
+ compatible = arm,armv8-pmuv3;
+ interrupts = 0 60 4,
+0 61 4,
+0 62 4,
+0 63 4;
+ };
+
+ smb {
+ compatible = simple-bus;
+
+ #address-cells = 2;
+ #size-cells = 1;
+ ranges = 0 0 0 0x0800 0x0400,
+1 0 0 0x1400 0x0400,
+2 0 0 0x1800 0x0400,
+3 0 0 0x1c00 0x0400,
+4 0 0 0x0c00 0x0400,
+5 0 0 0x1000 0x0400;
+
+ #interrupt-cells = 1;
+ interrupt-map-mask = 0 0 63;
+
[U-Boot] [PATCH v2 0/4] arm64 support
From: David Feng feng...@phytium.com.cn *** BLURB HERE *** David Feng (4): core support of arm64 board support of arm64 arch/lib support of arm64 arch/cpu and arch/include and arch/dts support of arm64 arch/arm64/config.mk| 32 +++ arch/arm64/cpu/armv8/Makefile | 51 arch/arm64/cpu/armv8/cache.S| 118 arch/arm64/cpu/armv8/config.mk | 29 ++ arch/arm64/cpu/armv8/cpu.c | 108 arch/arm64/cpu/armv8/exceptions.S | 208 ++ arch/arm64/cpu/armv8/start.S| 198 ++ arch/arm64/cpu/armv8/tlb.S | 38 +++ arch/arm64/cpu/u-boot.lds | 73 + arch/arm64/dts/aemv8a.dtsi | 234 arch/arm64/include/asm/arch-armv8/mmu.h | 117 arch/arm64/include/asm/atomic.h | 115 arch/arm64/include/asm/bitops.h | 153 +++ arch/arm64/include/asm/byteorder.h | 31 +++ arch/arm64/include/asm/cache.h | 53 arch/arm64/include/asm/config.h | 41 +++ arch/arm64/include/asm/errno.h |1 + arch/arm64/include/asm/global_data.h| 38 +++ arch/arm64/include/asm/gpio.h |1 + arch/arm64/include/asm/io.h | 193 + arch/arm64/include/asm/linkage.h| 49 arch/arm64/include/asm/posix_types.h| 61 + arch/arm64/include/asm/processor.h | 59 arch/arm64/include/asm/ptrace.h | 58 arch/arm64/include/asm/sections.h | 27 ++ arch/arm64/include/asm/string.h | 49 arch/arm64/include/asm/system.h | 106 +++ arch/arm64/include/asm/types.h | 67 + arch/arm64/include/asm/u-boot.h | 38 +++ arch/arm64/include/asm/unaligned.h | 28 ++ arch/arm64/include/asm/utils.h | 56 arch/arm64/lib/Makefile | 64 + arch/arm64/lib/board.c | 456 +++ arch/arm64/lib/bootm.c | 211 ++ arch/arm64/lib/cache.c | 282 +++ arch/arm64/lib/crt0.S | 129 + arch/arm64/lib/interrupts.c | 109 arch/arm64/lib/relocate.S | 72 + arch/arm64/lib/reset.c | 37 +++ arch/arm64/lib/timer.c | 95 +++ board/armltd/dts/vexpress64.dts | 215 +++ board/armltd/vexpress64/Makefile| 43 +++ board/armltd/vexpress64/vexpress64.c| 63 + boards.cfg |1 + common/cmd_bdinfo.c | 32 +++ common/fdt_support.c| 66 ++--- common/image.c |5 +- doc/README.arm64| 10 + examples/standalone/stubs.c | 13 + include/configs/vexpress_aemv8a.h | 200 ++ include/image.h |1 + lib/asm-offsets.c |4 - 52 files changed, 4500 insertions(+), 38 deletions(-) create mode 100644 arch/arm64/config.mk create mode 100644 arch/arm64/cpu/armv8/Makefile create mode 100644 arch/arm64/cpu/armv8/cache.S create mode 100644 arch/arm64/cpu/armv8/config.mk create mode 100644 arch/arm64/cpu/armv8/cpu.c create mode 100644 arch/arm64/cpu/armv8/exceptions.S create mode 100644 arch/arm64/cpu/armv8/start.S create mode 100644 arch/arm64/cpu/armv8/tlb.S create mode 100644 arch/arm64/cpu/u-boot.lds create mode 100644 arch/arm64/dts/aemv8a.dtsi create mode 100644 arch/arm64/include/asm/arch-armv8/mmu.h create mode 100644 arch/arm64/include/asm/atomic.h create mode 100644 arch/arm64/include/asm/bitops.h create mode 100644 arch/arm64/include/asm/byteorder.h create mode 100644 arch/arm64/include/asm/cache.h create mode 100644 arch/arm64/include/asm/config.h create mode 100644 arch/arm64/include/asm/errno.h create mode 100644 arch/arm64/include/asm/global_data.h create mode 100644 arch/arm64/include/asm/gpio.h create mode 100644 arch/arm64/include/asm/io.h create mode 100644 arch/arm64/include/asm/linkage.h create mode 100644 arch/arm64/include/asm/posix_types.h create mode 100644 arch/arm64/include/asm/processor.h create mode 100644 arch/arm64/include/asm/ptrace.h create mode 100644 arch/arm64/include/asm/sections.h create mode 100644 arch/arm64/include/asm/string.h create mode 100644 arch/arm64/include/asm/system.h create mode 100644 arch/arm64/include/asm/types.h create mode 100644 arch/arm64/include/asm/u-boot.h create mode 100644 arch/arm64/include/asm/unaligned.h create mode 100644 arch/arm64/include/asm/utils.h create mode 100644 arch/arm64/lib/Makefile create mode 100644 arch/arm64/lib/board.c create mode 100644 arch/arm64/lib/bootm.c create mode 100644 arch/arm64/lib/cache.c create mode 100644 arch/arm64/lib/crt0.S create mode 100644
Re: [U-Boot] [U-boot] U-Boot Driver Model question
Hi, On Wed, Aug 14, 2013 at 2:05 AM, tiger...@viatech.com.cn wrote: Hi, experts: I found U-Boot Driver Model introduction ppt at SLM2012 Conference. It seems current drivers in u-boot was still not implemented by this Driver Model? Version 3 was posted here: http://u-boot.10912.n7.nabble.com/PATCH-v3-0-16-Driver-model-implementation-tests-demo-and-GPIO-td157293.html I have some feedback which I intend to address in the next few weeks. It was just a long-term plan? Yes, but the short term plan is to get the basic infrastructure agreed and in so that we can start moving to it. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/4] arm64 support
Hi David, On Wed, Aug 14, 2013 at 4:58 AM, feng...@phytium.com.cn wrote: From: David Feng feng...@phytium.com.cn *** BLURB HERE *** David Feng (4): core support of arm64 board support of arm64 arch/lib support of arm64 arch/cpu and arch/include and arch/dts support of arm64 arch/arm64/config.mk| 32 +++ arch/arm64/cpu/armv8/Makefile | 51 arch/arm64/cpu/armv8/cache.S| 118 arch/arm64/cpu/armv8/config.mk | 29 ++ arch/arm64/cpu/armv8/cpu.c | 108 arch/arm64/cpu/armv8/exceptions.S | 208 ++ arch/arm64/cpu/armv8/start.S| 198 ++ arch/arm64/cpu/armv8/tlb.S | 38 +++ arch/arm64/cpu/u-boot.lds | 73 + arch/arm64/dts/aemv8a.dtsi | 234 arch/arm64/include/asm/arch-armv8/mmu.h | 117 arch/arm64/include/asm/atomic.h | 115 arch/arm64/include/asm/bitops.h | 153 +++ arch/arm64/include/asm/byteorder.h | 31 +++ arch/arm64/include/asm/cache.h | 53 arch/arm64/include/asm/config.h | 41 +++ arch/arm64/include/asm/errno.h |1 + arch/arm64/include/asm/global_data.h| 38 +++ arch/arm64/include/asm/gpio.h |1 + arch/arm64/include/asm/io.h | 193 + arch/arm64/include/asm/linkage.h| 49 arch/arm64/include/asm/posix_types.h| 61 + arch/arm64/include/asm/processor.h | 59 arch/arm64/include/asm/ptrace.h | 58 arch/arm64/include/asm/sections.h | 27 ++ arch/arm64/include/asm/string.h | 49 arch/arm64/include/asm/system.h | 106 +++ arch/arm64/include/asm/types.h | 67 + arch/arm64/include/asm/u-boot.h | 38 +++ arch/arm64/include/asm/unaligned.h | 28 ++ arch/arm64/include/asm/utils.h | 56 arch/arm64/lib/Makefile | 64 + arch/arm64/lib/board.c | 456 +++ Instead of this file, it would be good if you could make it use generic board - see CONFIG_SYS_GENERIC_BOARD in the README. It's great to see this work. arch/arm64/lib/bootm.c | 211 ++ arch/arm64/lib/cache.c | 282 +++ arch/arm64/lib/crt0.S | 129 + arch/arm64/lib/interrupts.c | 109 arch/arm64/lib/relocate.S | 72 + arch/arm64/lib/reset.c | 37 +++ arch/arm64/lib/timer.c | 95 +++ board/armltd/dts/vexpress64.dts | 215 +++ board/armltd/vexpress64/Makefile| 43 +++ board/armltd/vexpress64/vexpress64.c| 63 + boards.cfg |1 + common/cmd_bdinfo.c | 32 +++ common/fdt_support.c| 66 ++--- common/image.c |5 +- doc/README.arm64| 10 + examples/standalone/stubs.c | 13 + include/configs/vexpress_aemv8a.h | 200 ++ include/image.h |1 + lib/asm-offsets.c |4 - 52 files changed, 4500 insertions(+), 38 deletions(-) create mode 100644 arch/arm64/config.mk create mode 100644 arch/arm64/cpu/armv8/Makefile create mode 100644 arch/arm64/cpu/armv8/cache.S create mode 100644 arch/arm64/cpu/armv8/config.mk create mode 100644 arch/arm64/cpu/armv8/cpu.c create mode 100644 arch/arm64/cpu/armv8/exceptions.S create mode 100644 arch/arm64/cpu/armv8/start.S create mode 100644 arch/arm64/cpu/armv8/tlb.S create mode 100644 arch/arm64/cpu/u-boot.lds create mode 100644 arch/arm64/dts/aemv8a.dtsi create mode 100644 arch/arm64/include/asm/arch-armv8/mmu.h create mode 100644 arch/arm64/include/asm/atomic.h create mode 100644 arch/arm64/include/asm/bitops.h create mode 100644 arch/arm64/include/asm/byteorder.h create mode 100644 arch/arm64/include/asm/cache.h create mode 100644 arch/arm64/include/asm/config.h create mode 100644 arch/arm64/include/asm/errno.h create mode 100644 arch/arm64/include/asm/global_data.h create mode 100644 arch/arm64/include/asm/gpio.h create mode 100644 arch/arm64/include/asm/io.h create mode 100644 arch/arm64/include/asm/linkage.h create mode 100644 arch/arm64/include/asm/posix_types.h create mode 100644 arch/arm64/include/asm/processor.h create mode 100644 arch/arm64/include/asm/ptrace.h create mode 100644 arch/arm64/include/asm/sections.h create mode 100644 arch/arm64/include/asm/string.h create mode 100644 arch/arm64/include/asm/system.h create mode 100644 arch/arm64/include/asm/types.h create mode 100644 arch/arm64/include/asm/u-boot.h create mode 100644
Re: [U-Boot] [PATCH] i.MX: Add documentation on how to use SPI NOR on MX28evk
Hi Mårten, On 13/08/2013 17:48, Mårten Wikman wrote: 2013/8/11 Otavio Salvador ota...@ossystems.com.br: On Sun, Aug 11, 2013 at 10:49 AM, Mårten Wikman marten.wik...@novia.fi wrote: This adds necessary information on how to use U-boot on SPI NOR on MX28evk Signed-off-by: Marten Wikman marten.wik...@novia.fi Marten, The patch looks right and complete; I'd just split it in two patches: - add the new target - add documentation From your commit log it is not clear you're adding the new target. -- Otavio Salvador O.S. Systems http://www.ossystems.com.brhttp://projetos.ossystems.com.br Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750 Should I split it into two and send is as PATCH v2 to the mailing list? This is necessary - the two items documentation and new target are orthogonal. Please do it in this way. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/8] MIPS: bootm: fix checkpatch.pl warnings
2013.08.11. 21:39 keltezéssel, Daniel Schwierzeck írta: Signed-off-by: Daniel Schwierzeck daniel.schwierz...@gmail.com Looks good, but the subject line is misleading a bit. I would expect that the patch fixes all warnings, however there are some CamelCase warnings even after the patch. -Gabor ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/13/2013 10:31 PM, Zhang Ying-B40530 wrote: Hi, Tom, This patch hasn't been applied? I think it should be applied early and it is needed by other patches of this set. Thanks. I expect that as part of the overall series, once ready, York will take this and include it in his pull request, which is why I've given it my acked-by. -Original Message- From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Tom Rini Sent: Friday, June 28, 2013 5:57 AM To: Wood Scott-B07421 Cc: u-boot@lists.denx.de; Wood Scott-B07421; aflem...@gmail.com; Zhang Ying-B40530 Subject: Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import On Thu, Jun 27, 2013 at 03:16:34PM -0500, Scott Wood wrote: On 06/27/2013 07:17:48 AM, Tom Rini wrote: On Thu, Jun 27, 2013 at 02:35:34AM +, Zhang Ying-B40530 wrote: -Original Message- From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Tom Rini [snip] Building for am335x_evm and am335x_evm_usbspl should tell you if it is, or is not. Whacking network support into SPL required more than --gc-sections alone could give us and we needed to drop a few couldn't-ever-reach calls and functionality out. [Zhang Ying] Yes, I tried to build for am335x_evm without this ifdef, no problem. Whether it can be removed? Did you also build am335x_evm_usbspl? It builds OK for me with the ifdef removed. It adds 81 bytes to the SPL. I think we can live with that. Acked-by: Tom Rini tr...@ti.com -- Tom - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJSC4qaAAoJENk4IS6UOR1WekUP/1Z09OiAc2BHni42XWqAK9JB FvfQI82mHuI1eOSXa3hRT4wGpfuXaOhjydjXDoI6MNUvN3ZjxaE2EAPdr7oZX0ws DnRyKPOPHNyK3s/5CQWaKlCfDfxaL4a6mo4EYVsR+vMxJdcZr+wWBNNVwoWaAFU6 LDGlEwONt+m7fM6GGKRfFCfJ7iyBLks893Joitv7oAa2fOnnrto803Bpgq5IIaac IiEVaSznHfFEhtiaDhPRoUhhuYlgHfEYwSAMNm+FoxvIdKTus4EgBoTFXrbZRmzx Q9/SwS9FFKZrhKRj8xReB0Yn/wqWWdQFkuUknBnQENhzAXT+Qdr9J3EDYRBT1F9d KOrjmjZPgcbIrObhmeqAXb9qL5A1Tsa3v/Ap6RErdYwGoHSHhaAetfY3PqGagc3Z Yai9tJLqgrhuXYFqkcv9CIHhfwJC66nNZ+5bE3nAihjQW9Ny8soqTaoYQoC+MELM /AjEk/RAYXpSMW3dO9uS20VWEMaATIJ2cqHO04zAZcdvrYdTvRWmfGOYF8APYm1K 6JytRhTNf0Uh3Yatx7qpvBbNhT/mGAV7krUMQiAcRUg7FcAEIJFPawH4OEQx9yTF LAByOQ9BDRHErtON2gdksItJk3Sam4BwT1x1eeVq8fdzj2o/uTLIm5t63a53TdUd OnffrvuBulEjZQJCcq1h =tuhI -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/4] arm, am33xx: add defines for gmii_sel_register bits
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/14/2013 02:29 AM, Mugunthan V N wrote: On Monday 12 August 2013 11:06 PM, Mugunthan V N wrote: On Monday 12 August 2013 07:52 PM, Tom Rini wrote: +#define GMII2_SEL_MII 0x0 +#define GMII2_SEL_RMII 0x4 +#define GMII2_SEL_RGMII 0x8 +#define GMII2_SEL_NOTUSED 0xc NOTUSED not needed as it is not supposed to be used. same here ... I think Not Used in the TRM here means this port is not used rather than this combination of bits is not to be used, so the changes are correct. But having this define is not useful as far as I can think of as there is not abstraction API for this to check what user is passing. But I leave it to Tom's decision to have this change or not. Other than this the patch looks good to me. Acked-by: Mugunthan V N mugunthan...@ti.com I had a discussion with the hardware team internally and the comment is *When these bits are set to 11b the RGMII is selected with internal delay mode which was not timing closed. Therefore this register setting is not supported so it should not be used. The respective pin multiplexing should be used to deselect any unused CPGMAC pins.*c The same will be updated in the TRM soon. So can you remove NOTUSED define and resubmit the patch again and can include my Acked-by in your next version patch. Along with fixing the boards that set these bits to not set them please, thanks! - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJSC4tmAAoJENk4IS6UOR1Wn98P/ia2XzqBG//s8gxhKSn39QIb K2m3U/X1qiAFlibWhCgje6j7C1wBE0vHEn/ef/XP9+sCKRUZJHjFlaPKH4UO8l4d sMTPrz+n2OHpVPN/pQmc/tpA3D8KWHUo0OzIT3kvnonLyfUPT0qDEZ3qw1++1QmE 1LMqCQzubkrjJogN0TgzXYaKLG7IeGYev/XdaL8xRcpzsTz6DTlBDb62Inzidag2 yFY2Lb+/e0O7ji5iamevOdmniFEcXusQq2w98KavMxyeYG/TkKaMcWHegoayUmOC BJVUAbMQlRMsqzad9+w9x/TTDZ+Hb5jg8mTC61PmurWwOj99AbLgYipkVcIAScft TLO5bNHlDuj5Gk+4kU2R+5JAuPWLlKXTtmffsl6GLFcKHU0OsLGoPUGwVcn9SZax 1b0VG3ojFfk5hNRpQMaK6LUtQI6aPbr67GKP/1osJR0kZF2fTlRe9i/Sc1caJxhm GoHT7S+DbPA7pLFQfetz4V2EsHwe6IQuErhkG45Pia2zTzhjz05PGfKeRBubuuUH rjv6cwfamPfZ/OLzG0Ju61UHCVgVjbjUAkL84GYuAfsSttfxZYDVC37Rdyhx+MYm xSf0czR+q4qJaRWfwndCLNtcTrCP6OLKKSDer9CZkWNWSQnqBuMyUxlsWUrAyGpv daPZyMqV/kg5X47ToECn =txIN -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: OMAP: Enable 8-bit eMMC access for OMAP4/5/DRA7xx
Enable 8-bit host capability for HSMMC2 and/or HSMMC3. CONFIG_HSMMC2_8BIT
(for OMAP4/5/DRA7xx) and/or CONFIG_HSMMC3_8BIT (for DRA7xx only) must be
defined in the board header if an 8-bit eMMC device is connected to the
corresponding port.
Fix the No status update error that appeared for eMMC devices by
inserting a 20 us delay between writing arguments and command. This
solution has been proposed by Michael Cashwell mboa...@prograde.net.
A minor cosmetic fix in a comment as well.
Signed-off-by: Lubomir Popov lpo...@mm-sol.com
---
Tested on a custom OMAP5430 board with a SanDisk 8 GB eMMC, and on a TI
750-2172 Processor Board (with OMAP4460 ES1.1 and a 32 GB SanDisk eMMC),
mounted on a custom main board. Actual performance gain is negligible as
compared to 4-bit mode (about 2 ms faster FAT loading for a 4 MB image on
the 4460, that is in the range of 1%), but the advantage is that the eMMC
interface can be electrically validated in U-Boot.
drivers/mmc/omap_hsmmc.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 975b2c5..08e2c8b 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -376,6 +376,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd
*cmd,
}
writel(cmd-cmdarg, mmc_base-arg);
+ udelay(20); /* To fix No status update error on eMMC */
writel((cmd-cmdidx 24) | flags, mmc_base-cmd);
start = get_timer(0);
@@ -480,7 +481,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const
char *buf,
unsigned int count;
/*
-* Start Polled Read
+* Start Polled Write
*/
count = (size MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
count /= 4;
@@ -586,6 +587,8 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint
f_max, int cd_gpio,
{
struct mmc *mmc = hsmmc_dev[dev_index];
struct omap_hsmmc_data *priv_data = hsmmc_dev_data[dev_index];
+ uint host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
+MMC_MODE_HC;
sprintf(mmc-name, OMAP SD/MMC);
mmc-send_cmd = mmc_send_cmd;
@@ -600,11 +603,20 @@ int omap_mmc_init(int dev_index, uint host_caps_mask,
uint f_max, int cd_gpio,
#ifdef OMAP_HSMMC2_BASE
case 1:
priv_data-base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
+#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
+ defined(CONFIG_DRA7XX)) defined(CONFIG_HSMMC2_8BIT)
+ /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
+ host_caps_val |= MMC_MODE_8BIT;
+#endif
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
priv_data-base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
+#if defined(CONFIG_DRA7XX) defined(CONFIG_HSMMC3_8BIT)
+ /* Enable 8-bit interface for eMMC on DRA7XX */
+ host_caps_val |= MMC_MODE_8BIT;
+#endif
break;
#endif
default:
--
1.7.9.5
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[U-Boot] [PATCH v2 6/6] am335x_evm: am33xx_spl_board_init function and scale core frequency
Add a am33xx_spl_board_init (and enable the PMICs) that we may see,
depending on the board we are running on. In all cases, we see if we
can rely on the efuse_sma register to tell us the maximum speed. In the
case of Beaglebone White, we need to make sure we are on AC power, and
are on later than rev A1, and then we can ramp up to the PG1.0 maximum
of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that
supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we
cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we
need to rely on the efuse_sma if we are on PG2.1, and the defaults for
PG1.0/2.0.
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v2:
- Re-work into helper functions to determine max clock frequency, move
tps65910 probe / update into pmic_tps65910.c
---
arch/arm/cpu/armv7/am33xx/sys_info.c | 57 ++
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |8 ++
arch/arm/include/asm/arch-am33xx/sys_proto.h |3 +
board/ti/am335x/board.c | 126 ++
include/configs/am335x_evm.h |4 +
5 files changed, 198 insertions(+)
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c
b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 63afaaa..fbc01ac 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -17,6 +17,7 @@
#include asm/arch/sys_proto.h
#include asm/arch/cpu.h
#include asm/arch/clock.h
+#include power/tps65910.h
struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
@@ -119,3 +120,59 @@ int print_cpuinfo(void)
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_AM33XX
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
+{
+ int sil_rev;
+
+ sil_rev = readl(cdev-deviceid) 28;
+
+ if (sil_rev == 1)
+ /* PG 2.0, efuse may not be set. */
+ return MPUPLL_M_800;
+ else if (sil_rev = 2) {
+ /* Check what the efuse says our max speed is. */
+ int efuse_arm_mpu_max_freq;
+ efuse_arm_mpu_max_freq = readl(cdev-efuse_sma);
+ switch ((efuse_arm_mpu_max_freq DEVICE_ID_MASK)) {
+ case AM335X_ZCZ_1000:
+ return MPUPLL_M_1000;
+ case AM335X_ZCZ_800:
+ return MPUPLL_M_800;
+ case AM335X_ZCZ_720:
+ return MPUPLL_M_720;
+ case AM335X_ZCZ_600:
+ case AM335X_ZCE_600:
+ return MPUPLL_M_600;
+ case AM335X_ZCZ_300:
+ case AM335X_ZCE_300:
+ return MPUPLL_M_300;
+ }
+ }
+
+ /* PG 1.0 or otherwise unknown, use the PG1.0 max */
+ return MPUPLL_M_720;
+}
+
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
+{
+ /* For PG2.1 and later, we have one set of values. */
+ if (sil_rev = 2) {
+ switch (frequency) {
+ case MPUPLL_M_1000:
+ return TPS65910_OP_REG_SEL_1_3_2_5;
+ case MPUPLL_M_800:
+ return TPS65910_OP_REG_SEL_1_2_6;
+ case MPUPLL_M_720:
+ return TPS65910_OP_REG_SEL_1_2_0;
+ case MPUPLL_M_600:
+ case MPUPLL_M_300:
+ return TPS65910_OP_REG_SEL_1_1_3;
+ }
+ }
+
+ /* Default to PG1.0/PG2.0 values. */
+ return TPS65910_OP_REG_SEL_1_1_3;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 80e1899..789188b 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -16,6 +16,14 @@
#define CONFIG_SYS_MPUCLK 550
#endif
+/* MAIN PLL Fdll supported frequencies */
+#define MPUPLL_M_1000 1000
+#define MPUPLL_M_800 800
+#define MPUPLL_M_720 720
+#define MPUPLL_M_600 600
+#define MPUPLL_M_550 550
+#define MPUPLL_M_300 300
+
extern void pll_init(void);
extern void enable_emif_clocks(void);
extern void enable_dmm_clocks(void);
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h
b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 5a42efc..1340f83 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -10,6 +10,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include asm/arch/cpu.h
#define BOARD_REV_ID 0x0
@@ -38,4 +39,6 @@ void omap_nand_switch_ecc(uint32_t, uint32_t);
void rtc32k_enable(void);
void uart_soft_reset(void);
void am33xx_spl_board_init(void);
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
#endif
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 7138d73..e7f14db 100644
--- a/board/ti/am335x/board.c
+++
[U-Boot] [PATCH v2 5/6] am33xx: Add the efuse_sma CONTROL_MODULE register
Starting with PG2.1 we have a register in the CONTROL_MODULE that is set
with the package type and maximum supported frequency. Add this, and
the relevant mask/values.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/include/asm/arch-am33xx/cpu.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index bcb4c50..1021767 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -38,6 +38,16 @@
#define AM335X 0xB944
#define TI81XX 0xB81E
#define DEVICE_ID (CTRL_BASE + 0x0600)
+#define DEVICE_ID_MASK 0x1FFF
+
+/* MPU max frequencies */
+#define AM335X_ZCZ_300 0x1FEF
+#define AM335X_ZCZ_600 0x1FAF
+#define AM335X_ZCZ_720 0x1F2F
+#define AM335X_ZCZ_800 0x1E2F
+#define AM335X_ZCZ_10000x1C2F
+#define AM335X_ZCE_300 0x1FDF
+#define AM335X_ZCE_600 0x1F9F
/* This gives the status of the boot mode pins on the evm */
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
@@ -335,6 +345,8 @@ struct ctrl_dev {
unsigned int macid1h; /* offset 0x3c */
unsigned int resv4[4];
unsigned int miisel;/* offset 0x50 */
+ unsigned int resv5[106];
+ unsigned int efuse_sma; /* offset 0x1FC */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
--
1.7.9.5
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[U-Boot] [PATCH v2 3/6] drivers/power/pmic: Add tps65910 driver
From: Philip, Avinash avinashphi...@ti.com
Add a driver for the TPS65910 PMIC that is found in the AM335x GP EVM,
AM335x EVM SK and others.
Signed-off-by: Philip, Avinash avinashphi...@ti.com
[trini: Split and rework Avinash's changes into new drivers/power
framework]
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v2:
- Change to SPDX license tag
- Add TRM link in the header
- Add tps65910_set_i2c_control()
---
drivers/power/pmic/Makefile|1 +
drivers/power/pmic/pmic_tps65910.c | 83
include/power/tps65910.h | 75
3 files changed, 159 insertions(+)
create mode 100644 drivers/power/pmic/pmic_tps65910.c
create mode 100644 include/power/tps65910.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index ac2b625..11b3d03 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -14,6 +14,7 @@ COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
+COBJS-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/power/pmic/pmic_tps65910.c
b/drivers/power/pmic/pmic_tps65910.c
new file mode 100644
index 000..7ee1160
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65910.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, www.ti.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+#include power/tps65910.h
+
+/*
+ * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C
+ * interface.
+ * @return: 0 on success, not 0 on failure
+ */
+int tps65910_set_i2c_control(void)
+{
+ int ret;
+ uchar buf;
+
+ /* VDD1/2 voltage selection register access by control i/f */
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
+ buf, 1);
+
+ if (ret)
+ return ret;
+
+ buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
+
+ return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
+buf, 1);
+}
+
+/*
+ * tps65910_voltage_update() - Voltage switching for MPU frequency switching.
+ * @module: mpu - 0, core - 1
+ * @vddx_op_vol_sel: vdd voltage to set
+ * @return: 0 on success, not 0 on failure
+ */
+int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
+{
+ uchar buf;
+ unsigned int reg_offset;
+ int ret;
+
+ if (module == MPU)
+ reg_offset = TPS65910_VDD1_OP_REG;
+ else
+ reg_offset = TPS65910_VDD2_OP_REG;
+
+ /* Select VDDx OP */
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, buf, 1);
+ if (ret)
+ return ret;
+
+ buf = ~TPS65910_OP_REG_CMD_MASK;
+
+ ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, buf, 1);
+ if (ret)
+ return ret;
+
+ /* Configure VDDx OP Voltage */
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, buf, 1);
+ if (ret)
+ return ret;
+
+ buf = ~TPS65910_OP_REG_SEL_MASK;
+ buf |= vddx_op_vol_sel;
+
+ ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, buf, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, buf, 1);
+ if (ret)
+ return ret;
+
+ if ((buf TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel)
+ return 1;
+
+ return 0;
+}
diff --git a/include/power/tps65910.h b/include/power/tps65910.h
new file mode 100644
index 000..9600e9f
--- /dev/null
+++ b/include/power/tps65910.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, www.ti.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65910
+ */
+#ifndef __POWER_TPS65910_H__
+#define __POWER_TPS65910_H__
+
+#define MPU 0
+#define CORE1
+
+#define TPS65910_SR_I2C_ADDR 0x12
+#define TPS65910_CTRL_I2C_ADDR 0x2D
+
+/* PMIC Register offsets */
+#define TPS65910_VDD1_REG 0x21
+#define TPS65910_VDD1_OP_REG 0x22
+#define TPS65910_VDD2_REG 0x24
+#define TPS65910_VDD2_OP_REG 0x25
+#define TPS65910_DEVCTRL_REG 0x3F
+
+/* VDD2 VDD1 control register (VDD2_REG VDD1_REG) */
+#define TPS65910_VGAIN_SEL_MASK(0x3 6)
+#define TPS65910_ILMAX_MASK(0x1 5)
+#define TPS65910_TSTEP_MASK(0x7 2)
+#define TPS65910_ST_MASK
[U-Boot] [PATCH v2 1/6] spl/Makefile: Add drivers/power/pmic/libpmic to CONFIG_SPL_POWER_SUPPORT
We may need to access the PMIC code in SPL, when we have power set. Signed-off-by: Tom Rini tr...@ti.com --- spl/Makefile |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/spl/Makefile b/spl/Makefile index 6e5299b..dff1345 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -72,7 +72,8 @@ LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o -LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o +LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o \ + drivers/power/pmic/libpmic.o LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/6] drivers/power/pmic: Add tps65217 driver
From: Greg Guyotte gguyo...@ti.com
Add a driver for the TPS65217 PMIC that is found in the Beaglebone
family of boards.
Signed-off-by: Greg Guyotte gguyo...@ti.com
[trini: Split and rework Greg's changes into new drivers/power
framework]
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v2:
- Address Dan's comments
- Change to SPDX license tag
- Add TRM link in the header
Signed-off-by: Tom Rini tr...@ti.com
---
drivers/power/pmic/Makefile|1 +
drivers/power/pmic/pmic_tps65217.c | 109
include/power/tps65217.h | 79 ++
3 files changed, 189 insertions(+)
create mode 100644 drivers/power/pmic/pmic_tps65217.c
create mode 100644 include/power/tps65217.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index f054470..ac2b625 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -13,6 +13,7 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/power/pmic/pmic_tps65217.c
b/drivers/power/pmic/pmic_tps65217.c
new file mode 100644
index 000..36e9024
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65217.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, www.ti.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+#include power/tps65217.h
+
+/**
+ * tps65217_reg_read() - Generic function that can read a TPS65217 register
+ * @src_reg:Source register address
+ * @src_val:Address of destination variable
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65217_reg_read(uchar src_reg, uchar *src_val)
+{
+ return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1);
+}
+
+/**
+ * tps65217_reg_write() - Generic function that can write a TPS65217 PMIC
+ *register or bit field regardless of protection
+ *level.
+ *
+ * @prot_level: Register password protection. Use
+ *TPS65217_PROT_LEVEL_NONE,
+ *TPS65217_PROT_LEVEL_1 or TPS65217_PROT_LEVEL_2
+ * @dest_reg:Register address to write.
+ * @dest_val:Value to write.
+ * @mask:Bit mask (8 bits) to be applied. Function will only
+ *change bits that are set in the bit mask.
+ *
+ * @return: 0 for success, not 0 on failure, as per the i2c API
+ */
+int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+ uchar mask)
+{
+ uchar read_val;
+ uchar xor_reg;
+ int ret;
+
+ /*
+* If we are affecting only a bit field, read dest_reg and apply the
+* mask
+*/
+ if (mask != TPS65217_MASK_ALL_BITS) {
+ ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, read_val, 1);
+ if (ret)
+ return ret;
+ read_val = (~mask);
+ read_val |= (dest_val mask);
+ dest_val = read_val;
+ }
+
+ if (prot_level 0) {
+ xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK;
+ ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
+ xor_reg, 1);
+ if (ret)
+ return ret;
+ }
+
+ ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, dest_val, 1);
+ if (ret)
+ return ret;
+
+ if (prot_level == TPS65217_PROT_LEVEL_2) {
+ ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
+ xor_reg, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, dest_val, 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * tps65217_voltage_update() - Function to change a voltage level, as this
+ *is a multi-step process.
+ * @dc_cntrl_reg: DC voltage control register to change.
+ * @volt_sel: New value for the voltage register
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
+{
+ if ((dc_cntrl_reg != TPS65217_DEFDCDC1)
+ (dc_cntrl_reg != TPS65217_DEFDCDC2)
+ (dc_cntrl_reg != TPS65217_DEFDCDC3))
+ return 1;
+
+ /* set voltage level */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
+ TPS65217_MASK_ALL_BITS))
+ return 1;
+
+ /* set GO bit to initiate voltage transition */
+ if
[U-Boot] [PATCH v2 4/6] am33xx: Add am33xx_spl_board_init function, call
We need to allow for a further call-out in spl_board_init. Call this
am33xx_spl_board_init and add a __weak version. This function may be
used to scale the MPU frequency up, depending on board needs.
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v2:
- Move am33xx_spl_board_init to am33xx/board.c from
omap-common/boot-common.c
---
arch/arm/cpu/armv7/am33xx/board.c|9 +
arch/arm/cpu/armv7/omap-common/boot-common.c |3 +++
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
3 files changed, 13 insertions(+)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 07ab91c..88e2093 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -27,6 +27,7 @@
#include miiphy.h
#include cpsw.h
#include asm/errno.h
+#include linux/compiler.h
#include linux/usb/ch9.h
#include linux/usb/gadget.h
#include linux/usb/musb.h
@@ -143,6 +144,14 @@ int arch_misc_init(void)
}
#ifdef CONFIG_SPL_BUILD
+/*
+ * This function is the place to do per-board things such as ramp up the
+ * MPU clock frequency.
+ */
+__weak void am33xx_spl_board_init(void)
+{
+}
+
void rtc32k_enable(void)
{
struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c
b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 6b9ce36..32293a1 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -75,6 +75,9 @@ void spl_board_init(void)
#if defined(CONFIG_AM33XX) defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
arch_misc_init();
#endif
+#ifdef CONFIG_AM33XX
+ am33xx_spl_board_init();
+#endif
}
int board_mmc_init(bd_t *bis)
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h
b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 1424f90..5a42efc 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -37,4 +37,5 @@ void omap_nand_switch_ecc(uint32_t, uint32_t);
void rtc32k_enable(void);
void uart_soft_reset(void);
+void am33xx_spl_board_init(void);
#endif
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] am335x:Handle worst case scenario for Errata 1.0.24
From: Steve Kipisz s-kipi...@ti.com
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
the boot ROM sets the frequencies for OPP100. This patch attempts to
drop the frequencies back to OPP50 as soon as possible in the SPL. Then
later the voltages and frequencies up set higher.
Cc: Enric Balletbo i Serra eballe...@iseebcn.com
Cc: Lars Poeschel poesc...@lemonage.de
Signed-off-by: Steve Kipisz s-kipi...@ti.com
[trini: Adapt to current framework]
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v2:
- Address Dan Murphy's comments
---
arch/arm/cpu/armv7/am33xx/board.c|2 +
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 72 ++
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |3 +
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
board/ti/am335x/board.c | 12
include/configs/pcm051.h |1 +
include/power/tps65217.h |1 +
7 files changed, 68 insertions(+), 24 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 88e2093..e94b038 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -150,6 +150,8 @@ int arch_misc_init(void)
*/
__weak void am33xx_spl_board_init(void)
{
+ mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+ core_pll_config(OPP_100);
}
void rtc32k_enable(void)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index fb3fb43..f623004 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -42,12 +42,17 @@
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000
+#define COREPLL_M_OPP50 50
#define COREPLL_N (OSC-1)
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
+#define COREPLL_M4_OPP50 1
+#define COREPLL_M5_OPP50 1
+#define COREPLL_M6_OPP50 1
+
/*
* USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
* frequency needs to be set to 960 MHZ. Hence,
@@ -266,12 +271,7 @@ void mpu_pll_config_val(int mpull_m)
;
}
-static void mpu_pll_config(void)
-{
- mpu_pll_config_val(CONFIG_SYS_MPUCLK);
-}
-
-static void core_pll_config(void)
+void core_pll_config(int opp)
{
u32 clkmode, clksel, div_m4, div_m5, div_m6;
@@ -285,29 +285,53 @@ static void core_pll_config(void)
writel(PLL_BYPASS_MODE, cmwkup-clkmoddpllcore);
while (readl(cmwkup-idlestdpllcore) != ST_MN_BYPASS)
- ;
+ ;
+ if (opp == OPP_50) {
+ clksel = clksel (~CLK_SEL_MASK);
+ clksel = clksel | ((COREPLL_M_OPP50 CLK_SEL_SHIFT)
+ | COREPLL_N);
+ writel(clksel, cmwkup-clkseldpllcore);
- clksel = clksel (~CLK_SEL_MASK);
- clksel = clksel | ((COREPLL_M CLK_SEL_SHIFT) | COREPLL_N);
- writel(clksel, cmwkup-clkseldpllcore);
+ div_m4 = div_m4 ~CLK_DIV_MASK;
+ div_m4 = div_m4 | COREPLL_M4_OPP50;
+ writel(div_m4, cmwkup-divm4dpllcore);
- div_m4 = div_m4 ~CLK_DIV_MASK;
- div_m4 = div_m4 | COREPLL_M4;
- writel(div_m4, cmwkup-divm4dpllcore);
+ div_m5 = div_m5 ~CLK_DIV_MASK;
+ div_m5 = div_m5 | COREPLL_M5_OPP50;
+ writel(div_m5, cmwkup-divm5dpllcore);
- div_m5 = div_m5 ~CLK_DIV_MASK;
- div_m5 = div_m5 | COREPLL_M5;
- writel(div_m5, cmwkup-divm5dpllcore);
+ div_m6 = div_m6 ~CLK_DIV_MASK;
+ div_m6 = div_m6 | COREPLL_M6_OPP50;
+ writel(div_m6, cmwkup-divm6dpllcore);
- div_m6 = div_m6 ~CLK_DIV_MASK;
- div_m6 = div_m6 | COREPLL_M6;
- writel(div_m6, cmwkup-divm6dpllcore);
+ clkmode = clkmode | CLK_MODE_SEL;
+ writel(clkmode, cmwkup-clkmoddpllcore);
- clkmode = clkmode | CLK_MODE_SEL;
- writel(clkmode, cmwkup-clkmoddpllcore);
+ while (readl(cmwkup-idlestdpllcore) != ST_DPLL_CLK)
+ ;
+ } else {
+ clksel = clksel (~CLK_SEL_MASK);
+ clksel = clksel | ((COREPLL_M CLK_SEL_SHIFT) | COREPLL_N);
+ writel(clksel, cmwkup-clkseldpllcore);
+
+ div_m4 = div_m4 ~CLK_DIV_MASK;
+ div_m4 = div_m4 | COREPLL_M4;
+ writel(div_m4, cmwkup-divm4dpllcore);
+
+ div_m5 = div_m5 ~CLK_DIV_MASK;
+ div_m5 = div_m5 | COREPLL_M5;
+ writel(div_m5, cmwkup-divm5dpllcore);
+
+ div_m6 = div_m6 ~CLK_DIV_MASK;
+ div_m6 = div_m6 | COREPLL_M6;
+ writel(div_m6, cmwkup-divm6dpllcore);
+
+ clkmode = clkmode | CLK_MODE_SEL;
+
[U-Boot] [PATCH v3 6/6] am335x_evm: am33xx_spl_board_init function and scale core frequency
Add a am33xx_spl_board_init (and enable the PMICs) that we may see,
depending on the board we are running on. In all cases, we see if we
can rely on the efuse_sma register to tell us the maximum speed. In the
case of Beaglebone White, we need to make sure we are on AC power, and
are on later than rev A1, and then we can ramp up to the PG1.0 maximum
of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that
supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we
cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we
need to rely on the efuse_sma if we are on PG2.1, and the defaults for
PG1.0/2.0.
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v3:
- Set sil_rev in tps65910 case
Changes in v2:
- Re-work into helper functions to determine max clock frequency, move
tps65910 probe / update into pmic_tps65910.c
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/sys_info.c | 57 ++
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |8 ++
arch/arm/include/asm/arch-am33xx/sys_proto.h |3 +
board/ti/am335x/board.c | 127 ++
include/configs/am335x_evm.h |4 +
5 files changed, 199 insertions(+)
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c
b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 63afaaa..fbc01ac 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -17,6 +17,7 @@
#include asm/arch/sys_proto.h
#include asm/arch/cpu.h
#include asm/arch/clock.h
+#include power/tps65910.h
struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
@@ -119,3 +120,59 @@ int print_cpuinfo(void)
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_AM33XX
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
+{
+ int sil_rev;
+
+ sil_rev = readl(cdev-deviceid) 28;
+
+ if (sil_rev == 1)
+ /* PG 2.0, efuse may not be set. */
+ return MPUPLL_M_800;
+ else if (sil_rev = 2) {
+ /* Check what the efuse says our max speed is. */
+ int efuse_arm_mpu_max_freq;
+ efuse_arm_mpu_max_freq = readl(cdev-efuse_sma);
+ switch ((efuse_arm_mpu_max_freq DEVICE_ID_MASK)) {
+ case AM335X_ZCZ_1000:
+ return MPUPLL_M_1000;
+ case AM335X_ZCZ_800:
+ return MPUPLL_M_800;
+ case AM335X_ZCZ_720:
+ return MPUPLL_M_720;
+ case AM335X_ZCZ_600:
+ case AM335X_ZCE_600:
+ return MPUPLL_M_600;
+ case AM335X_ZCZ_300:
+ case AM335X_ZCE_300:
+ return MPUPLL_M_300;
+ }
+ }
+
+ /* PG 1.0 or otherwise unknown, use the PG1.0 max */
+ return MPUPLL_M_720;
+}
+
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
+{
+ /* For PG2.1 and later, we have one set of values. */
+ if (sil_rev = 2) {
+ switch (frequency) {
+ case MPUPLL_M_1000:
+ return TPS65910_OP_REG_SEL_1_3_2_5;
+ case MPUPLL_M_800:
+ return TPS65910_OP_REG_SEL_1_2_6;
+ case MPUPLL_M_720:
+ return TPS65910_OP_REG_SEL_1_2_0;
+ case MPUPLL_M_600:
+ case MPUPLL_M_300:
+ return TPS65910_OP_REG_SEL_1_1_3;
+ }
+ }
+
+ /* Default to PG1.0/PG2.0 values. */
+ return TPS65910_OP_REG_SEL_1_1_3;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 80e1899..789188b 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -16,6 +16,14 @@
#define CONFIG_SYS_MPUCLK 550
#endif
+/* MAIN PLL Fdll supported frequencies */
+#define MPUPLL_M_1000 1000
+#define MPUPLL_M_800 800
+#define MPUPLL_M_720 720
+#define MPUPLL_M_600 600
+#define MPUPLL_M_550 550
+#define MPUPLL_M_300 300
+
extern void pll_init(void);
extern void enable_emif_clocks(void);
extern void enable_dmm_clocks(void);
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h
b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 5a42efc..1340f83 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -10,6 +10,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include asm/arch/cpu.h
#define BOARD_REV_ID 0x0
@@ -38,4 +39,6 @@ void omap_nand_switch_ecc(uint32_t, uint32_t);
void rtc32k_enable(void);
void uart_soft_reset(void);
void am33xx_spl_board_init(void);
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
#endif
diff --git a/board/ti/am335x/board.c
Re: [U-Boot] [PATCH v2 2/6] drivers/power/pmic: Add tps65217 driver
Hi Tom, Greg
From: Greg Guyotte gguyo...@ti.com
Add a driver for the TPS65217 PMIC that is found in the Beaglebone
family of boards.
Signed-off-by: Greg Guyotte gguyo...@ti.com
[trini: Split and rework Greg's changes into new drivers/power
framework]
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v2:
- Address Dan's comments
- Change to SPDX license tag
- Add TRM link in the header
Signed-off-by: Tom Rini tr...@ti.com
---
drivers/power/pmic/Makefile|1 +
drivers/power/pmic/pmic_tps65217.c | 109
include/power/tps65217.h | 79 ++
3 files changed, 189 insertions(+) create mode 100644
drivers/power/pmic/pmic_tps65217.c create mode 100644
include/power/tps65217.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index f054470..ac2b625 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -13,6 +13,7 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
COBJS:= $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/power/pmic/pmic_tps65217.c
b/drivers/power/pmic/pmic_tps65217.c new file mode 100644
index 000..36e9024
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65217.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+#include power/tps65217.h
+
+/**
+ * tps65217_reg_read() - Generic function that can read a TPS65217
register
+ * @src_reg: Source register address
+ * @src_val: Address of destination variable
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65217_reg_read(uchar src_reg, uchar *src_val)
+{
+ return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1);
Would it be possible to comply with pmic driver model?
It can be found at ./drivers/power/power_core.c
Moreover the generic function for reading/writing data to/from pmic is
already defined at ./drivers/power/power_{i2c|spi}.c
Maybe it would be possible to use/modify the already available code?
+}
+
+/**
+ * tps65217_reg_write() - Generic function that can write a
TPS65217 PMIC
+ * register or bit field regardless of
protection
+ * level.
+ *
+ * @prot_level:Register password protection. Use
+ * TPS65217_PROT_LEVEL_NONE,
+ * TPS65217_PROT_LEVEL_1 or
TPS65217_PROT_LEVEL_2
+ * @dest_reg: Register address to write.
+ * @dest_val: Value to write.
+ * @mask: Bit mask (8 bits) to be applied.
Function will only
+ * change bits that are set in the bit
mask.
+ *
+ * @return:0 for success, not 0 on failure, as
per the i2c API
+ */
+int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar
dest_val,
The same as above.
+uchar mask)
+{
+ uchar read_val;
+ uchar xor_reg;
+ int ret;
+
+ /*
+ * If we are affecting only a bit field, read dest_reg and
apply the
+ * mask
+ */
+ if (mask != TPS65217_MASK_ALL_BITS) {
+ ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1,
read_val, 1);
+ if (ret)
+ return ret;
+ read_val = (~mask);
+ read_val |= (dest_val mask);
+ dest_val = read_val;
+ }
+
+ if (prot_level 0) {
+ xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK;
+ ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD,
1,
+ xor_reg, 1);
+ if (ret)
+ return ret;
+ }
+
+ ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, dest_val, 1);
+ if (ret)
+ return ret;
+
+ if (prot_level == TPS65217_PROT_LEVEL_2) {
+ ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD,
1,
+ xor_reg, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1,
dest_val, 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * tps65217_voltage_update() - Function to change a voltage level,
as this
+ * is a multi-step process.
+ * @dc_cntrl_reg: DC voltage control register to
change.
+ * @volt_sel: New value for the voltage
register
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
Maybe pmic_set_output() method from
Re: [U-Boot] [PATCH v2 3/6] drivers/power/pmic: Add tps65910 driver
Hi Tom, Philip,
I have the same comments as with:
[PATCH v2 2/6] drivers/power/pmic: Add tps65217 driver
From: Philip, Avinash avinashphi...@ti.com
Add a driver for the TPS65910 PMIC that is found in the AM335x GP EVM,
AM335x EVM SK and others.
Signed-off-by: Philip, Avinash avinashphi...@ti.com
[trini: Split and rework Avinash's changes into new drivers/power
framework]
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v2:
- Change to SPDX license tag
- Add TRM link in the header
- Add tps65910_set_i2c_control()
---
drivers/power/pmic/Makefile|1 +
drivers/power/pmic/pmic_tps65910.c | 83
include/power/tps65910.h | 75
3 files changed, 159 insertions(+)
create mode 100644 drivers/power/pmic/pmic_tps65910.c create mode
100644 include/power/tps65910.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index ac2b625..11b3d03 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -14,6 +14,7 @@ COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
+COBJS-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
COBJS:= $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/power/pmic/pmic_tps65910.c
b/drivers/power/pmic/pmic_tps65910.c new file mode 100644
index 000..7ee1160
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65910.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+#include power/tps65910.h
+
+/*
+ * tps65910_set_i2c_control() - Set the TPS65910 to be controlled
via the I2C
+ * interface.
+ * @return: 0 on success, not 0 on failure
+ */
+int tps65910_set_i2c_control(void)
+{
+ int ret;
+ uchar buf;
+
+ /* VDD1/2 voltage selection register access by control i/f */
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG,
1,
+buf, 1);
+
+ if (ret)
+ return ret;
+
+ buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
+
+ return i2c_write(TPS65910_CTRL_I2C_ADDR,
TPS65910_DEVCTRL_REG, 1,
+ buf, 1);
+}
+
+/*
+ * tps65910_voltage_update() - Voltage switching for MPU frequency
switching.
+ * @module: mpu - 0, core - 1
+ * @vddx_op_vol_sel:vdd voltage to set
+ * @return: 0 on success, not 0 on failure
+ */
+int tps65910_voltage_update(unsigned int module, unsigned char
vddx_op_vol_sel) +{
+ uchar buf;
+ unsigned int reg_offset;
+ int ret;
+
+ if (module == MPU)
+ reg_offset = TPS65910_VDD1_OP_REG;
+ else
+ reg_offset = TPS65910_VDD2_OP_REG;
+
+ /* Select VDDx OP */
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, buf,
1);
+ if (ret)
+ return ret;
+
+ buf = ~TPS65910_OP_REG_CMD_MASK;
+
+ ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, buf,
1);
+ if (ret)
+ return ret;
+
+ /* Configure VDDx OP Voltage */
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, buf,
1);
+ if (ret)
+ return ret;
+
+ buf = ~TPS65910_OP_REG_SEL_MASK;
+ buf |= vddx_op_vol_sel;
+
+ ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, buf,
1);
+ if (ret)
+ return ret;
+
+ ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, buf,
1);
+ if (ret)
+ return ret;
+
+ if ((buf TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel)
+ return 1;
+
+ return 0;
+}
diff --git a/include/power/tps65910.h b/include/power/tps65910.h
new file mode 100644
index 000..9600e9f
--- /dev/null
+++ b/include/power/tps65910.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * For more details, please see the TRM at
http://www.ti.com/product/tps65910
+ */
+#ifndef __POWER_TPS65910_H__
+#define __POWER_TPS65910_H__
+
+#define MPU 0
+#define CORE1
+
+#define TPS65910_SR_I2C_ADDR 0x12
+#define TPS65910_CTRL_I2C_ADDR 0x2D
+
+/* PMIC Register offsets */
+#define TPS65910_VDD1_REG0x21
+#define TPS65910_VDD1_OP_REG 0x22
+#define TPS65910_VDD2_REG0x24
+#define TPS65910_VDD2_OP_REG 0x25
+#define TPS65910_DEVCTRL_REG 0x3F
+
+/* VDD2 VDD1 control register (VDD2_REG VDD1_REG) */
+#define TPS65910_VGAIN_SEL_MASK (0x3
6) +#define
Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import
On 08/14/2013 06:48 AM, Tom Rini wrote: On 08/13/2013 10:31 PM, Zhang Ying-B40530 wrote: Hi, Tom, This patch hasn't been applied? I think it should be applied early and it is needed by other patches of this set. Thanks. I expect that as part of the overall series, once ready, York will take this and include it in his pull request, which is why I've given it my acked-by. Ying, This patch fell through the crack. I didn't see it because it was marked as superseded. Please check your other patches. You can delegate them to me. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/6] drivers/power/pmic: Add tps65217 driver
On Wed, Aug 14, 2013 at 05:08:12PM +0200, Lukasz Majewski wrote:
Hi Tom, Greg
From: Greg Guyotte gguyo...@ti.com
Add a driver for the TPS65217 PMIC that is found in the Beaglebone
family of boards.
Signed-off-by: Greg Guyotte gguyo...@ti.com
[trini: Split and rework Greg's changes into new drivers/power
framework]
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v2:
- Address Dan's comments
- Change to SPDX license tag
- Add TRM link in the header
Signed-off-by: Tom Rini tr...@ti.com
---
drivers/power/pmic/Makefile|1 +
drivers/power/pmic/pmic_tps65217.c | 109
include/power/tps65217.h | 79 ++
3 files changed, 189 insertions(+) create mode 100644
drivers/power/pmic/pmic_tps65217.c create mode 100644
include/power/tps65217.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index f054470..ac2b625 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -13,6 +13,7 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/power/pmic/pmic_tps65217.c
b/drivers/power/pmic/pmic_tps65217.c new file mode 100644
index 000..36e9024
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65217.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, www.ti.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+#include power/tps65217.h
+
+/**
+ * tps65217_reg_read() - Generic function that can read a TPS65217
register
+ * @src_reg:Source register address
+ * @src_val:Address of destination variable
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65217_reg_read(uchar src_reg, uchar *src_val)
+{
+ return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1);
Would it be possible to comply with pmic driver model?
It can be found at ./drivers/power/power_core.c
At the high level, not yet. We don't have battery support (but fixing
that to be optional in the core wouldn't be hard) but the general pmic
code assumes one pmic charger per binary. We need both in the same
binary (since we decide at run-time if it's one of the boards with 65910
or 65217).
Moreover the generic function for reading/writing data to/from pmic is
already defined at ./drivers/power/power_{i2c|spi}.c
Maybe it would be possible to use/modify the already available code?
Without the MAX family datasheets handy, I'm not sure how exactly the
tx_num stuff maps to the password concept the TI parts have. Skimming
the kernel mfd drivers implies to me that logic ends up being per-chip
(or at least vendor).
[snip]
+/**
+ * tps65217_voltage_update() - Function to change a voltage level,
as this
+ *is a multi-step process.
+ * @dc_cntrl_reg: DC voltage control register to
change.
+ * @volt_sel: New value for the voltage
register
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
Maybe pmic_set_output() method from ./drivers/power/power_core.c can be
reused?
I'm not sure.
[snip]
+#define TPS65217_SEQ6 0x1E
Shouldn't the above registers be defined as enum?
For example at ./include/power/max8997_pmic.h
/* MAX 8997 registers */
enum {
MAX8997_REG_PMIC_ID0= 0x00,
MAX8997_REG_PMIC_ID1= 0x01,
MAX8997_REG_INTSRC = 0x02,
PMIC_NUM_OF_REGS
I assume it's a style thing I've overlooked, so sure, not a problem in
general.
--
Tom
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Re: [U-Boot] [PATCH] RFC: tegra: Avoid using I2C prior to relocation
On 08/13/2013 03:12 PM, Tom Rini wrote: On Wed, Aug 07, 2013 at 10:20:01AM -0600, Stephen Warren wrote: On 08/06/2013 11:52 PM, Simon Glass wrote: Tegra recently moved to the new I2C framework, which sets up I2C prior to relocation, and prior to calling i2c_init_board(). This causes a crash on Tegra boards. note: There are many ways to fix this. I believe this is one. It disables i2c_init() until relocation is complete. I have been unable to test it so far due to problems getting my Seaboard to work. I will try another Tegra board, but send this for comment in the meantime. Tested-by: Stephen Warren swar...@nvidia.com With a hand-tweaked commit message, applied to u-boot/master, thanks! Thanks! For the record, I tested u-boot.git/master commit: cdce889 tegra: Avoid using I2C prior to relocation on Beaver, and booted a kernel both from SD card and over USB Ethernet, and both cases worked fine. So, we have a known-good commit for any future bisects:-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] ARM: OMAP: Enable 8-bit eMMC access for OMAP4/5/DRA7xx
Enable 8-bit host capability for HSMMC2 and/or HSMMC3. CONFIG_HSMMC2_8BIT
(for OMAP4/5/DRA7xx) and/or CONFIG_HSMMC3_8BIT (for DRA7xx only) must be
defined in the board header if an 8-bit eMMC device is connected to the
corresponding port.
Fix the No status update error that appeared for eMMC devices by
inserting a 20 us delay between writing arguments and command. This
solution has been proposed by Michael Cashwell mboa...@prograde.net.
A minor cosmetic fix in a comment as well.
Signed-off-by: Lubomir Popov lpo...@mm-sol.com
---
V2 fixes the actual write to mmc-host_caps (missed in V1; tests were
performed with U-Boot 2013.04, where it was patched initially).
Tested on a custom OMAP5430 board with a SanDisk 8 GB eMMC, and on a TI
750-2172 Processor Board (with OMAP4460 ES1.1 and a 32 GB SanDisk eMMC),
mounted on a custom main board. Actual performance gain is negligible as
compared to 4-bit mode (about 2 ms faster FAT loading for a 4 MB image on
the 4460, that is in the range of 1%), but the advantage is that the eMMC
interface can be electrically validated in U-Boot.
drivers/mmc/omap_hsmmc.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 975b2c5..9a0d7c9 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -376,6 +376,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd
*cmd,
}
writel(cmd-cmdarg, mmc_base-arg);
+ udelay(20); /* To fix No status update error on eMMC */
writel((cmd-cmdidx 24) | flags, mmc_base-cmd);
start = get_timer(0);
@@ -480,7 +481,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const
char *buf,
unsigned int count;
/*
-* Start Polled Read
+* Start Polled Write
*/
count = (size MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
count /= 4;
@@ -586,6 +587,8 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint
f_max, int cd_gpio,
{
struct mmc *mmc = hsmmc_dev[dev_index];
struct omap_hsmmc_data *priv_data = hsmmc_dev_data[dev_index];
+ uint host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
+MMC_MODE_HC;
sprintf(mmc-name, OMAP SD/MMC);
mmc-send_cmd = mmc_send_cmd;
@@ -600,11 +603,20 @@ int omap_mmc_init(int dev_index, uint host_caps_mask,
uint f_max, int cd_gpio,
#ifdef OMAP_HSMMC2_BASE
case 1:
priv_data-base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
+#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
+ defined(CONFIG_DRA7XX)) defined(CONFIG_HSMMC2_8BIT)
+ /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
+ host_caps_val |= MMC_MODE_8BIT;
+#endif
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
priv_data-base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
+#if defined(CONFIG_DRA7XX) defined(CONFIG_HSMMC3_8BIT)
+ /* Enable 8-bit interface for eMMC on DRA7XX */
+ host_caps_val |= MMC_MODE_8BIT;
+#endif
break;
#endif
default:
@@ -620,8 +632,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint
f_max, int cd_gpio,
mmc-getwp = omap_mmc_getwp;
mmc-voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- mmc-host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
- MMC_MODE_HC) ~host_caps_mask;
+ mmc-host_caps = host_caps_val ~host_caps_mask;
mmc-f_min = 40;
--
1.7.9.5
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Re: [U-Boot] [PATCH] RFC: tegra: Avoid using I2C prior to relocation
Hi Stephen, On Wed, Aug 14, 2013 at 9:59 AM, Stephen Warren swar...@wwwdotorg.org wrote: On 08/13/2013 03:12 PM, Tom Rini wrote: On Wed, Aug 07, 2013 at 10:20:01AM -0600, Stephen Warren wrote: On 08/06/2013 11:52 PM, Simon Glass wrote: Tegra recently moved to the new I2C framework, which sets up I2C prior to relocation, and prior to calling i2c_init_board(). This causes a crash on Tegra boards. note: There are many ways to fix this. I believe this is one. It disables i2c_init() until relocation is complete. I have been unable to test it so far due to problems getting my Seaboard to work. I will try another Tegra board, but send this for comment in the meantime. Tested-by: Stephen Warren swar...@nvidia.com With a hand-tweaked commit message, applied to u-boot/master, thanks! Thanks! For the record, I tested u-boot.git/master commit: cdce889 tegra: Avoid using I2C prior to relocation on Beaver, and booted a kernel both from SD card and over USB Ethernet, and both cases worked fine. So, we have a known-good commit for any future bisects:-) OK that's good, thanks. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific
On 07/18/2013 01:13 PM, Thierry Reding wrote: From: Thierry Reding tred...@nvidia.com Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file. Tom, can these two patches be applied please? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH REPOST] ARM: tegra: support raw ramdisks
From: Stephen Warren swar...@nvidia.com This way, we don't have to run mkimage on them. Signed-off-by: Stephen Warren swar...@nvidia.com --- include/configs/tegra-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index ccd68a1..8b275a7 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -135,6 +135,7 @@ #define CONFIG_CMD_GPIO #define CONFIG_CMD_ENTERRCM #define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD /* Defines for SPL */ #define CONFIG_SPL -- 1.8.1.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH REPOST] ARM: tegra: support raw ramdisks
On Wed, Aug 14, 2013 at 10:05 AM, Stephen Warren swar...@wwwdotorg.org wrote: From: Stephen Warren swar...@nvidia.com This way, we don't have to run mkimage on them. Signed-off-by: Stephen Warren swar...@nvidia.com Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific
Sure, your mkimage patch, and Thierry's 2 cache patches have been applied to u-boot-tegra/next (after rebasing next against Albert's ARM master), build tested (all Tegra boards build fine), and pushed to denx. Also updated u-boot-tegra/master w/Albert's ARM TOT. Sorry for the delay, really busy w/new stuff. Ping me if I get behind again. Thanks, Tom -Original Message- From: Stephen Warren [mailto:swar...@wwwdotorg.org] Sent: Wednesday, August 14, 2013 9:05 AM To: Tom Warren Cc: Thierry Reding; u-boot@lists.denx.de; Thierry Reding; Stephen Warren Subject: Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific On 07/18/2013 01:13 PM, Thierry Reding wrote: From: Thierry Reding tred...@nvidia.com Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file. Tom, can these two patches be applied please? --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/6] handle compression buffer overflows
Hi Kees, On Mon, Aug 12, 2013 at 5:01 PM, Kees Cook keesc...@chromium.org wrote: [sending, now subscribed so mailman won't yell at me] This series fixes gzip, lzma, and lzo to not overflow when writing to output buffers. Without this, it might be possible for untrusted compressed input to overflow the buffers used to hold the decompressed image. To catch these conditions, I added a series of compression tests available in the sandbox build. Without the fixes in patches 3, 4, and 5, the overflows are visible. It is on patchwork so I think all is well. BTW I see these warnings that we should fix sometime (not in your code) $ crosfw -b sandbox Configuring for sandbox board... cmd_bootm.c: In function ‘bootm_load_os’: cmd_bootm.c:443:11: warning: passing argument 4 of ‘lzop_decompress’ from incompatible pointer type [enabled by default] /home/sjg/c/src/third_party/u-boot/files/include/linux/lzo.h:31:5: note: expected ‘size_t *’ but argument is of type ‘uint *’ cmd_ximg.c: In function ‘do_imgextract’: cmd_ximg.c:225:6: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] cmd_ximg.c:225:14: warning: ‘hdr’ may be used uninitialized in this function [-Wuninitialized] Also do you have a diffstat for your cover letter? If you use patman for the cover letter too it should happy automatically. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] sandbox: add compression tests
Hi Kees, On Mon, Aug 12, 2013 at 4:48 PM, Kees Cook keesc...@chromium.org wrote: This adds the test_compression command when building the sandbox. This tests the existing compression and decompression routines for simple sanity and for buffer overflow conditions. Signed-off-by: Kees Cook keesc...@chromium.org --- include/configs/sandbox.h |5 + test/Makefile |1 + test/compression.c| 384 + 3 files changed, 390 insertions(+) create mode 100644 test/compression.c diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 98dd083..b7fe14d 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -125,4 +125,9 @@ stdout=serial\0 \ stderr=serial\0 +#define CONFIG_GZIP_COMPRESSED +#define CONFIG_BZIP2 +#define CONFIG_LZO +#define CONFIG_LZMA + #endif diff --git a/test/Makefile b/test/Makefile index 83594f3..ede113d 100644 --- a/test/Makefile +++ b/test/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB= $(obj)libtest.o COBJS-$(CONFIG_SANDBOX) += command_ut.o +COBJS-$(CONFIG_SANDBOX) += compression.o COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/test/compression.c b/test/compression.c new file mode 100644 index 000..c78c8e4 --- /dev/null +++ b/test/compression.c @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2013, The Chromium Authors + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA I believe we are moving to a new license structure, although I'm not sure how this affects new patches. See Licenses/README. + */ + +#define DEBUG + +#include common.h +#include command.h +#include malloc.h + +#include u-boot/zlib.h +#include bzlib.h + +#ifdef CONFIG_LZMA +#include lzma/LzmaTypes.h +#include lzma/LzmaDec.h +#include lzma/LzmaTools.h +#endif /* CONFIG_LZMA */ + +#ifdef CONFIG_LZO +#include linux/lzo.h +#endif /* CONFIG_LZO */ You shouldn't need these #ifdefs. + +static const char plain[] = + I am a highly compressable bit of text.\n + I am a highly compressable bit of text.\n + I am a highly compressable bit of text.\n + There are many like me, but this one is mine.\n + If I were any shorter, there wouldn't be much sense in\n + compressing me in the first place. At least with lzo, anyway,\n + which appears to behave poorly in the face of short text\n + messages.\n; + +/* bzip2 -c /tmp/plain.txt /tmp/plain.bz2 */ +static const char bzip2_compressed[] = + \x42\x5a\x68\x39\x31\x41\x59\x26\x53\x59\xe5\x63\xdd\x09\x00\x00 + \x28\x57\x80\x00\x10\x40\x85\x20\x20\x04\x00\x3f\xef\xdf\xf0\x30 + \x00\xd6\xd0\x34\x91\x89\xa6\xf5\x4d\x19\x1a\x19\x0d\x02\x34\xd4 + \xc9\x00\x34\x34\x00\x02\x48\x41\x35\x4f\xd4\xc6\x88\xd3\x50\x3d + \x4f\x51\x82\x4f\x88\xc3\x0d\x05\x62\x4f\x91\xa3\x52\x1b\xd0\x52 + \x41\x4a\xa3\x98\xc2\x6b\xca\xa3\x82\xa5\xac\x8b\x15\x99\x68\xad + \xdf\x29\xd6\xf1\xf7\x5a\x10\xcd\x8c\x26\x61\x94\x95\xfe\x9e\x16 + \x18\x28\x69\xd4\x23\x64\xcc\x2b\xe5\xe8\x5f\x00\xa4\x70\x26\x2c + \xee\xbd\x59\x6d\x6a\xec\xfc\x31\xda\x59\x0a\x14\x2a\x60\x1c\xf0 + \x04\x86\x73\x9a\xc5\x5b\x87\x3f\x5b\x4c\x93\xe6\xb5\x35\x0d\xa6 + \xb1\x2e\x62\x7b\xab\x67\xe7\x99\x2a\x14\x5e\x9f\x64\xcb\x96\xf4 + \x0d\x65\xd4\x39\xe6\x8b\x7e\xea\x1c\x03\x69\x97\x83\x58\x91\x96 + \xe1\xf0\x9d\xa4\x15\x8b\xb8\xc6\x93\xdc\x3d\xd9\x3c\x22\x55\xef + \xfb\xbb\x2a\xd3\x87\xa2\x8b\x04\xd9\x19\xf8\xe2\xfd\x4f\xdb\x1a + \x07\xc8\x60\xa3\x3f\xf8\xbb\x92\x29\xc2\x84\x87\x2b\x1e\xe8\x48; +static const unsigned long bzip2_compressed_size = 240; + +/* lzma -z -c /tmp/plain.txt /tmp/plain.lzma */ +static const char lzma_compressed[] = + \x5d\x00\x00\x80\x00\xff\xff\xff\xff\xff\xff\xff\xff\x00\x24\x88 + \x08\x26\xd8\x41\xff\x99\xc8\xcf\x66\x3d\x80\xac\xba\x17\xf1\xc8 + \xb9\xdf\x49\x37\xb1\x68\xa0\x2a\xdd\x63\xd1\xa7\xa3\x66\xf8\x15 + \xef\xa6\x67\x8a\x14\x18\x80\xcb\xc7\xb1\xcb\x84\x6a\xb2\x51\x16 +
Re: [U-Boot] [PATCH 2/6] documentation: add more compression configs
Hi Kees, On Mon, Aug 12, 2013 at 5:02 PM, Kees Cook keesc...@chromium.org wrote: This adds the missing compression config items to the README. Signed-off-by: Kees Cook keesc...@chromium.org --- README |9 + 1 file changed, 9 insertions(+) diff --git a/README b/README index 5c343da..247b8f3 100644 --- a/README +++ b/README @@ -1669,6 +1669,10 @@ CBFS (Coreboot Filesystem) support to compress the specified memory at its best effort. - Compression support: + CONFIG_GZIP + + Enabled by default for gzip compressed images. s/for/to support/ perhaps + CONFIG_BZIP2 If this option is set, support for bzip2 compressed @@ -1702,6 +1706,11 @@ CBFS (Coreboot Filesystem) support then calculate the amount of needed dynamic memory (ensuring the appropriate CONFIG_SYS_MALLOC_LEN value). + CONFIG_LZO + + If this option is set, support for LZO compressed images + is included. + - MII/PHY support: CONFIG_PHY_ADDR -- 1.7.9.5 Regards, Simon On Mon, Aug 12, 2013 at 5:02 PM, Kees Cook keesc...@chromium.org wrote: This adds the missing compression config items to the README. Signed-off-by: Kees Cook keesc...@chromium.org --- README |9 + 1 file changed, 9 insertions(+) diff --git a/README b/README index 5c343da..247b8f3 100644 --- a/README +++ b/README @@ -1669,6 +1669,10 @@ CBFS (Coreboot Filesystem) support to compress the specified memory at its best effort. - Compression support: + CONFIG_GZIP + + Enabled by default for gzip compressed images. + CONFIG_BZIP2 If this option is set, support for bzip2 compressed @@ -1702,6 +1706,11 @@ CBFS (Coreboot Filesystem) support then calculate the amount of needed dynamic memory (ensuring the appropriate CONFIG_SYS_MALLOC_LEN value). + CONFIG_LZO + + If this option is set, support for LZO compressed images + is included. + - MII/PHY support: CONFIG_PHY_ADDR -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/6] gzip: correctly bounds-check output buffer
On Mon, Aug 12, 2013 at 5:02 PM, Kees Cook keesc...@chromium.org wrote: The output buffer size not be reset by the gzip decoder or there is a risk of overflowing memory during decompression. Signed-off-by: Kees Cook keesc...@chromium.org Looks right to me. Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] lzma: correctly bounds-check output buffer
On Mon, Aug 12, 2013 at 5:02 PM, Kees Cook keesc...@chromium.org wrote: The output buffer size must be correctly passed to the lzma decoder or there is a risk of overflowing memory during decompression. Switching to the LZMA_FINISH_END mode means nothing is left in an unknown state once the buffer becomes full. Signed-off-by: Kees Cook keesc...@chromium.org Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/6] lzo: correctly bounds-check output buffer
On Mon, Aug 12, 2013 at 5:02 PM, Kees Cook keesc...@chromium.org wrote: This checks the size of the output buffer and fails if it was going to overflow the buffer during lzo decompression. Signed-off-by: Kees Cook keesc...@chromium.org Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] bootm: correctly bounds-check decompression
Hi Kees, On Mon, Aug 12, 2013 at 5:02 PM, Kees Cook keesc...@chromium.org wrote: This passes the actual memory allocation size for the destination to the decompression routines, avoiding potential memory overflows. Signed-off-by: Kees Cook keesc...@chromium.org Acked-by: Simon Glass s...@chromium.org (doesn't actually change the result since this parameter is ignored, but it is certainly cleaner, thank you) Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH]fsl/usb: Move USB internal phy definitions to fsl_usb.h
On 08/05/2013 03:30 AM, Ramneek Mehresh wrote: snip diff --git a/include/fsl_usb.h b/include/fsl_usb.h new file mode 100644 index 000..88d6a1f --- /dev/null +++ b/include/fsl_usb.h @@ -0,0 +1,80 @@ +/* + * Freescale USB Controller + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + Mehresh, I am trying to apply this patch and clean up the license header with SPDX license identifier. I noticed you are using GPL v2. As most of u-boot code uses GPL v2+ (with very few files under GPL v2), do you have a specific reason to stay with v2? If not, I am going to replace it with GPL v2.0+. Regards, York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mkimage: add option for adding dtc binary path via argument
On May 6, 2013, at 8:59 AM, Luka Perkov l...@openwrt.org wrote:
On Mon, May 06, 2013 at 02:32:51PM +0200, Wolfgang Denk wrote:
It appears there is no really good reason for this patch, so I think
we should drop it.
Ok. Thanks for the review.
Would there be any objection to adding an option to pass source paths to dtc
from mkimage? Currently, in order to do that, I have to find the source for
mkimage, grab the default dtc options out of mkimage.h and then pass that set
on the command line. It would be nice and only slightly more future proof if I
could just pass the source file search paths separately.
local t=${VSD_PATH}/app/flasher/uboot_flasher
local t2=${t}/tools
PATH=${t2}:$PATH ${t2}/mkimage -D -I dts -O dtb -p 500 -i ${release_dir} \
-f ${t}/update_field_mode.its spot_update.bin
I'd like to pass one or more paths like ${release_dir} without having to pass
(or even know about) -I dts -O dtb -p 500.
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[U-Boot] [PATCH v2 1/4] ARM: make reserving the gd register a make variable
Currently all ARM targets spell out that r8 needs to be a reserved register, while using a common crt0.s. Move this to a common make variable so it is not repeated (and can be easily changed) cc: Albert ARIBAUD albert.u.b...@aribaud.net Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl --- arch/arm/config.mk | 2 ++ arch/arm/cpu/arm1136/config.mk | 2 +- arch/arm/cpu/arm1176/config.mk | 2 +- arch/arm/cpu/arm720t/config.mk | 2 +- arch/arm/cpu/arm920t/config.mk | 2 +- arch/arm/cpu/arm925t/config.mk | 2 +- arch/arm/cpu/arm926ejs/config.mk | 2 +- arch/arm/cpu/arm946es/config.mk | 2 +- arch/arm/cpu/arm_intcm/config.mk | 2 +- arch/arm/cpu/armv7/config.mk | 2 +- arch/arm/cpu/armv7/rmobile/config.mk | 2 +- arch/arm/cpu/ixp/config.mk | 2 +- arch/arm/cpu/pxa/config.mk | 2 +- arch/arm/cpu/s3c44b0/config.mk | 2 +- arch/arm/cpu/sa1100/config.mk| 2 +- 15 files changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 540a119..5e382ab 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -98,3 +98,5 @@ endif ifneq ($(CONFIG_SPL_BUILD),y) ALL-y += checkarmreloc endif + +OPTION_FIXED_GD=$(call cc-option, -ffixed-r8) diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk index 1ef6061..daca1bd 100644 --- a/arch/arm/cpu/arm1136/config.mk +++ b/arch/arm/cpu/arm1136/config.mk @@ -4,7 +4,7 @@ # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float +PLATFORM_RELFLAGS += -fno-common $(OPTION_FIXED_GD) -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk index 917da03..163778a 100644 --- a/arch/arm/cpu/arm1176/config.mk +++ b/arch/arm/cpu/arm1176/config.mk @@ -4,7 +4,7 @@ # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float +PLATFORM_RELFLAGS += -fno-common $(OPTION_FIXED_GD) -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5t diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk index 56b6280..f1fb6a8 100644 --- a/arch/arm/cpu/arm720t/config.mk +++ b/arch/arm/cpu/arm720t/config.mk @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float +PLATFORM_RELFLAGS += -fno-common $(OPTION_FIXED_GD) -msoft-float PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi # = diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk index 58fd756..a6b2c6f 100644 --- a/arch/arm/cpu/arm920t/config.mk +++ b/arch/arm/cpu/arm920t/config.mk @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float +PLATFORM_RELFLAGS += -fno-common $(OPTION_FIXED_GD) -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # = diff --git a/arch/arm/cpu/arm925t/config.mk b/arch/arm/cpu/arm925t/config.mk index 58fd756..a6b2c6f 100644 --- a/arch/arm/cpu/arm925t/config.mk +++ b/arch/arm/cpu/arm925t/config.mk @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float +PLATFORM_RELFLAGS += -fno-common $(OPTION_FIXED_GD) -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # = diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 917ff7e..a29634d 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float +PLATFORM_RELFLAGS += -fno-common $(OPTION_FIXED_GD) -msoft-float PLATFORM_CPPFLAGS += -march=armv5te # = diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk index 1e41c11..7465da1 100644 --- a/arch/arm/cpu/arm946es/config.mk +++ b/arch/arm/cpu/arm946es/config.mk @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float +PLATFORM_RELFLAGS += -fno-common $(OPTION_FIXED_GD) -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # = diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk index 1e41c11..7465da1 100644 --- a/arch/arm/cpu/arm_intcm/config.mk +++ b/arch/arm/cpu/arm_intcm/config.mk @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
[U-Boot] [PATCH v2 0/4] ARM: use r9 for gd instead of r8
v2: update the README as requested by Wolfgang Denk cc: w...@denx.de Jeroen Hofstee (4): ARM: make reserving the gd register a make variable ARM,relocate: do not use r9 ARM: use r9 for gd README: update ARM register usage README | 8 +--- arch/arm/config.mk | 2 ++ arch/arm/cpu/arm1136/config.mk | 2 +- arch/arm/cpu/arm1176/config.mk | 2 +- arch/arm/cpu/arm720t/config.mk | 2 +- arch/arm/cpu/arm920t/config.mk | 2 +- arch/arm/cpu/arm925t/config.mk | 2 +- arch/arm/cpu/arm926ejs/config.mk | 2 +- arch/arm/cpu/arm946es/config.mk | 2 +- arch/arm/cpu/arm_intcm/config.mk | 2 +- arch/arm/cpu/armv7/config.mk | 2 +- arch/arm/cpu/armv7/rmobile/config.mk | 2 +- arch/arm/cpu/ixp/config.mk | 2 +- arch/arm/cpu/pxa/config.mk | 2 +- arch/arm/cpu/s3c44b0/config.mk | 2 +- arch/arm/cpu/sa1100/config.mk| 2 +- arch/arm/include/asm/global_data.h | 2 +- arch/arm/lib/crt0.S | 16 arch/arm/lib/relocate.S | 6 +++--- 19 files changed, 33 insertions(+), 29 deletions(-) -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] README: update ARM register usage
Besides the change of this patchset it also updates the README to reflect that GOT-generated relocations are no longer supported on ARM. cc: Albert ARIBAUD albert.u.b...@aribaud.net Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl --- README | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/README b/README index 3918807..d8af074 100644 --- a/README +++ b/README @@ -5534,15 +5534,17 @@ On ARM, the following registers are used: R0: function argument word/integer result R1-R3: function argument word - R9: GOT pointer - R10:stack limit (used only if stack checking if enabled) + R9: platform specific + R10:stack limit (used only if stack checking is enabled) R11:argument (frame) pointer R12:temporary workspace R13:stack pointer R14:link register R15:program counter -== U-Boot will use R8 to hold a pointer to the global data +== U-Boot will use R9 to hold a pointer to the global data + +Note: on ARM, only R_ARM_RELATIVE relocations are supported. On Nios II, the ABI is documented here: http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/4] ARM,relocate: do not use r9
r9 is a platform-specific register in ARM EABI and not per definition a general purpose register. Do not use it while relocating so it can be used for gd. cc: Albert ARIBAUD albert.u.b...@aribaud.net Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl --- arch/arm/lib/relocate.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index ab90430..a62a556 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -22,7 +22,7 @@ ENTRY(relocate_code) ldr r1, =__image_copy_start /* r1 - SRC __image_copy_start */ - subsr9, r0, r1 /* r9 - relocation offset */ + subsr4, r0, r1 /* r4 - relocation offset */ beq relocate_done /* skip relocation */ ldr r2, =__image_copy_end /* r2 - SRC __image_copy_end */ @@ -44,9 +44,9 @@ fixloop: bne fixnext /* relative fix: increase location by offset */ - add r0, r0, r9 + add r0, r0, r4 ldr r1, [r0] - add r1, r1, r9 + add r1, r1, r4 str r1, [r0] fixnext: cmp r2, r3 -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/4] ARM: use r9 for gd
To be more EABI compliant and as a preparation for building
with clang, use the platform-specific r9 register for gd
instead of r8.
note: The FIQ is not updated since it is not used in u-boot,
and under discussion for the time being.
The following checkpatch warning is ignored:
WARNING: Use of volatile is usually wrong: see
Documentation/volatile-considered-harmful.txt
cc: Albert ARIBAUD albert.u.b...@aribaud.net
Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl
---
arch/arm/config.mk | 2 +-
arch/arm/include/asm/global_data.h | 2 +-
arch/arm/lib/crt0.S| 16
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 5e382ab..5f6e032 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -99,4 +99,4 @@ ifneq ($(CONFIG_SPL_BUILD),y)
ALL-y += checkarmreloc
endif
-OPTION_FIXED_GD=$(call cc-option, -ffixed-r8)
+OPTION_FIXED_GD=$(call cc-option, -ffixed-r9)
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 79a9597..e126436 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -47,6 +47,6 @@ struct arch_global_data {
#include asm-generic/global_data.h
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm (r8)
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm (r9)
#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 960d12e..ac54b93 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -69,7 +69,7 @@ ENTRY(_main)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
sub sp, #GD_SIZE/* allocate one GD above SP */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- mov r8, sp /* GD is above SP */
+ mov r9, sp /* GD is above SP */
mov r0, #0
bl board_init_f
@@ -81,15 +81,15 @@ ENTRY(_main)
* 'here' but relocated.
*/
- ldr sp, [r8, #GD_START_ADDR_SP] /* sp = gd-start_addr_sp */
+ ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd-start_addr_sp */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r8, [r8, #GD_BD]/* r8 = gd-bd */
- sub r8, r8, #GD_SIZE/* new GD is below bd */
+ ldr r9, [r9, #GD_BD]/* r9 = gd-bd */
+ sub r9, r9, #GD_SIZE/* new GD is below bd */
adr lr, here
- ldr r0, [r8, #GD_RELOC_OFF] /* r0 = gd-reloc_off */
+ ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd-reloc_off */
add lr, lr, r0
- ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd-relocaddr */
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
b relocate_code
here:
@@ -111,8 +111,8 @@ clbss_l:cmp r0, r1 /* while not at end of
BSS */
bl red_led_on
/* call board_init_r(gd_t *id, ulong dest_addr) */
- mov r0, r8 /* gd_t */
- ldr r1, [r8, #GD_RELOCADDR] /* dest_addr */
+ mov r0, r9 /* gd_t */
+ ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */
/* call board_init_r */
ldr pc, =board_init_r /* this is auto-relocated! */
--
1.8.1.2
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[U-Boot] [PATCH] include/fsl_usb.h: Cleanup license header
Replace license header with SPDX license identifier. Replace GPL-2.0 with GPL-2.0+. Signed-off-by: York Sun york...@freescale.com --- include/fsl_usb.h | 18 +- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 88d6a1f..915774c 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -3,23 +3,7 @@ * * Copyright 2013 Freescale Semiconductor, Inc. * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier:GPL-2.0+ */ #ifndef _ASM_FSL_USB_H_ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mkimage: add option for adding dtc binary path via argument
Hi,
On Wed, Aug 14, 2013 at 10:58 AM, Harvey Chapman hchap...@3gfp.com wrote:
On May 6, 2013, at 8:59 AM, Luka Perkov l...@openwrt.org wrote:
On Mon, May 06, 2013 at 02:32:51PM +0200, Wolfgang Denk wrote:
It appears there is no really good reason for this patch, so I think
we should drop it.
Ok. Thanks for the review.
Would there be any objection to adding an option to pass source paths to dtc
from mkimage? Currently, in order to do that, I have to find the source for
mkimage, grab the default dtc options out of mkimage.h and then pass that set
on the command line. It would be nice and only slightly more future proof if
I could just pass the source file search paths separately.
So you mean the -i option? I think that would be valuable, yes.
Without it you need to put all your files in one directory, or
maintain the same directory structure in your release directory. It
gets really ugly. The -i option was added to deal with this and I
think it makes sense to make it available in mkimage.
local t=${VSD_PATH}/app/flasher/uboot_flasher
local t2=${t}/tools
PATH=${t2}:$PATH ${t2}/mkimage -D -I dts -O dtb -p 500 -i ${release_dir} \
-f ${t}/update_field_mode.its spot_update.bin
I'd like to pass one or more paths like ${release_dir} without having to
pass (or even know about) -I dts -O dtb -p 500.
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Re: [U-Boot] [PATCH] part1 of arm64. This patch provide u-boot with arm64 support. Currently it works on Foundation Model for armv8 or Fast Model for armv8.
On Wed, 2013-08-14 at 12:43 +0800, FengHua wrote:
-原始邮件-
发件人: Scott Wood scottw...@freescale.com
发送时间: 2013年8月14日 星期三
收件人: feng...@phytium.com.cn
抄送: u-boot@lists.denx.de, tr...@ti.com
主题: Re: [U-Boot] [PATCH] part1 of arm64. This patch provide u-boot with
arm64 support. Currently it works on Foundation Model for armv8 or Fast
Model for armv8.
On Mon, 2013-08-12 at 00:05 +0800, feng...@phytium.com.cn wrote:
diff --git a/arch/arm64/config.mk b/arch/arm64/config.mk
new file mode 100644
index 000..e40e983
--- /dev/null
+++ b/arch/arm64/config.mk
Does there really need to be a separate arch/arm64? I know this is what
Linux does, but on every other 32/64 architecture that decision has been
eventually reversed (even on x86, which has about as much difference
between 32 and 64 bit as ARM does).
We started working on armv8 U-Boot using a unified arch/arm, and at
least got to the point of something that builds, so it doesn't seem
impractical. Besides making maintenance easier, it would also make it
much easier to review what is being done differently for arm64 (and for
any files that do need to be moved or copied, be sure to pass -M -C to
git format-patch).
The porting is performed as a seperate architecture due to a few
considerations,
1. The porting will be simple and clear.
No, it's the opposite. It's hard to review what you changed from arm to
arm64.
2. There's no any real chip of armv8 until now. Many aspect of armv8 are
not completely confirmed.
I'm not sure why that makes a difference.
Of course, it could be merged with ARM at a proper time in the later.
Actually, linux kernel follow this mode.
Let's do it the right way from the start.
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2013 FengHua feng...@phytium.com.cn
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CROSS_COMPILE ?=
/home/fenghua/DS-5-Workspace/gcc-linaro-aarch64-linux-gnu-4.8-2013.05_linux/bin/aarch64-linux-gnu-
Please don't insert references to paths that only work on your computer.
I will fix it.
Plus, what about native builds that don't need a cross compiler?
Currently, there's no real chip of armv8. so,cross compiler is needed.
Eventually there will be (or someone could be masochistic enough to
build inside the emulator). The point remains that default
CROSS_COMPILE is a bad idea.
diff --git a/common/fdt_support.c b/common/fdt_support.c
index b034c98..9bc5821 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -21,6 +21,34 @@
*/
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Get cells len in bytes
+ * if #-cells property is 2 then len is 8
+ * otherwise len is 4
+ */
+static int get_cells_len(void *blob, char *nr_cells_name)
+{
+ const fdt32_t *cell;
+
+ cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
+ if (cell fdt32_to_cpu(*cell) == 2)
+ return 8;
+
+ return 4;
+}
+
+/*
+ * Write a 4 or 8 byte big endian cell
+ */
+static void write_cell(u8 *addr, u64 val, int size)
+{
+ int shift = (size - 1) * 8;
+ while (size-- 0) {
+ *addr++ = (val shift) 0xff;
+ shift -= 8;
+ }
+}
+
/**
* fdt_getprop_u32_default - Find a node and return it's property or a
default
*
@@ -131,9 +159,9 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff)
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int
force)
{
- int nodeoffset;
+ int nodeoffset, addr_cell_len;
int err, j, total;
- fdt32_t tmp;
+ fdt64_t tmp;
const char *path;
uint64_t addr, size;
@@ -170,9 +198,11 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong
initrd_end, int force)
return err;
}
+ addr_cell_len = get_cells_len(fdt, #address-cells);
+
path = fdt_getprop(fdt, nodeoffset, linux,initrd-start, NULL);
if ((path == NULL) || force) {
- tmp = cpu_to_fdt32(initrd_start);
+ write_cell((u8 *)tmp, initrd_start, addr_cell_len);
err
Re: [U-Boot] [PATCH] include/fsl_usb.h: Cleanup license header
Acked. -Ramneek -Original Message- From: sun york-R58495 Sent: Wednesday, August 14, 2013 11:56 PM To: Mehresh Ramneek-B31383 Cc: u-boot@lists.denx.de; sun york-R58495 Subject: [PATCH] include/fsl_usb.h: Cleanup license header Replace license header with SPDX license identifier. Replace GPL-2.0 with GPL-2.0+. Signed-off-by: York Sun york...@freescale.com --- include/fsl_usb.h | 18 +- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 88d6a1f..915774c 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -3,23 +3,7 @@ * * Copyright 2013 Freescale Semiconductor, Inc. * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier:GPL-2.0+ */ #ifndef _ASM_FSL_USB_H_ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-mpc85xx
Tom, The following changes since commit b98d934128bcd98106e764d2f492ac79c38ae53d: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2013-08-13 09:14:02 -0400) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to 49d87b1325fde11ebac60d8dc1cbd4c2c11d3973: include/fsl_usb.h: Cleanup license header (2013-08-14 11:29:51 -0700) Po Liu (1): powerpc/c29xpcie: add readme document for c29xpcie Prabhakar Kushwaha (1): powerpc/mpc85xx:Avoid hardcoded init for serdes block 1 2 York Sun (1): include/fsl_usb.h: Cleanup license header ramneek mehresh (2): fsl/usb: Move USB internal phy definitions to fsl_usb.h powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env variables arch/powerpc/cpu/mpc85xx/cpu_init.c|7 +- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 16 arch/powerpc/cpu/mpc8xxx/fdt.c | 22 -- arch/powerpc/include/asm/config_mpc85xx.h |4 + arch/powerpc/include/asm/immap_85xx.h | 48 board/freescale/c29xpcie/README| 100 include/fsl_usb.h | 64 +++ 7 files changed, 188 insertions(+), 73 deletions(-) create mode 100644 board/freescale/c29xpcie/README create mode 100644 include/fsl_usb.h I am still working on the remaining patches. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC][PATCH v4] ARM: mxs: Added application UART driver
Dear Andreas Wass,
The driver makes it possible to use an application UART as
the U-Boot output console for Freescale i.MX23/i.MX28 devices.
Signed-off-by: Andreas Wass andreas.w...@dalelven.com
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Marek Vasut ma...@denx.de
---
Changes for v2:
- Added comment that regs-uartapp.h is pulled from LTIB
- BM_ prefixes removed and _MASK suffixes added instead
- BP_ prefixes removed and _OFFSET suffixes added instead
- BF_ defines removed altogether
- CONFIG_MXS_AUART_CLK renamed to MXS_AUART_CLK and guarding ifndef
removed - Added comments describing what is set and unset during init of
driver - Added newline that was accidently removed from serial.c
Changes for v3:
- All BV_ values are now on the form (value something)
- BV_ prefix removed and double underscore substituted with a single
- File comment of mxs_auart.c now attributes what the driver is based on
- Uses gd-baudrate instead of CONFIG_BAUDRATE
- If gd-baudrate is 0 it reverts back to CONFIG_BAUDRATE
- Checks the validity of the div value calculated when setting the
baudrate - Magic numbers are now defines instead
- Cleanup of comments
- Cleanup of commit message
Changes for v4:
- Fixed UARTAPP_LINECTRL2_WLEN_*BITS values
drivers/serial/Makefile | 1 +
drivers/serial/mxs_auart.c | 151
drivers/serial/serial.c | 2 +
4 files changed, 403 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mxs/regs-uartapp.h
create mode 100644 drivers/serial/mxs_auart.c
diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h
b/arch/arm/include/asm/arch-mxs/regs-uartapp.h new file mode 100644
index 000..abd62c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
@@ -0,0 +1,249 @@
+/*
+ * Freescale MXS UARTAPP Register Definitions
+ *
+ * Copyright (C) 2013 Andreas Wass andreas.w...@dalelven.com
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM___MXS_UARTAPP_H
+#define __ARCH_ARM___MXS_UARTAPP_H
+
+#include asm/imx-common/regs-common.h
+
+#ifndef __ASSEMBLY__
+struct mxs_uartapp_regs {
+ mxs_reg_32(hw_uartapp_ctrl0)
+ mxs_reg_32(hw_uartapp_ctrl1)
+ mxs_reg_32(hw_uartapp_ctrl2)
+ mxs_reg_32(hw_uartapp_linectrl)
+ mxs_reg_32(hw_uartapp_linectrl2)
+ mxs_reg_32(hw_uartapp_intr)
+ mxs_reg_32(hw_uartapp_data)
+ mxs_reg_32(hw_uartapp_stat)
+ mxs_reg_32(hw_uartapp_debug)
+ mxs_reg_32(hw_uartapp_version)
+ mxs_reg_32(hw_uartapp_autobaud)
+};
+#endif
+
+
+#define UARTAPP_CTRL0_SFTRST_MASK(1 31)
+#define UARTAPP_CTRL0_CLKGATE_MASK (1 30)
+#define UARTAPP_CTRL0_RUN_MASK (1 29)
+#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 28)
+#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 27)
+#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET (1 4)
+#define UARTAPP_CTRL0_RXTIMEOUT_MASK 0x07FF
+#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0
+#define UARTAPP_CTRL0_XFER_COUNT_MASK0x
Two minor nits, replace this with 0x
+#define UARTAPP_CTRL1_RSVD2_OFFSET 29
+#define UARTAPP_CTRL1_RSVD2_MASK 0xE000
+
+#define UARTAPP_CTRL1_RUN_MASK (1 28)
+#define UARTAPP_CTRL1_RSVD1_OFFSET 16
+#define UARTAPP_CTRL1_RSVD1_MASK 0x0FFF
Here this would be (0xfff 16) to keep consistent.
Moreover, you can drop the RSVD portions.
[...]
The rest is good.
Best regards,
Marek Vasut
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Re: [U-Boot] [RFC][PATCH v4] ARM: mxs: Added application UART driver
Hi Andreas, On Wed, Aug 14, 2013 at 4:20 PM, Marek Vasut ma...@denx.de wrote: The rest is good. You could remove the RFC tag in your next submission. Also, it would be nice to add a mx28evk target that could make use of this driver, otherwise this will be just dead code, as there is no board setting CONFIG_MXS_AUART. If someone wants to use mx28evk with the console in the AUART port: make mx28evk_auart_console. This should be a second patch though. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC][PATCH v4] ARM: mxs: Added application UART driver
Dear Fabio Estevam, Hi Andreas, On Wed, Aug 14, 2013 at 4:20 PM, Marek Vasut ma...@denx.de wrote: The rest is good. You could remove the RFC tag in your next submission. Yes Also, it would be nice to add a mx28evk target that could make use of this driver, otherwise this will be just dead code, as there is no board setting CONFIG_MXS_AUART. In a separate patch. btw. it will colide with DUART code. If someone wants to use mx28evk with the console in the AUART port: make mx28evk_auart_console. This should be a second patch though. Yes Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] net: phy/realtek: Add support for RTL8211DN and RTL8211E phy modules
Hi York,
I guess with Andy no longer there as FSL u-boot maintainer, will the patch below
go through you or Joe. If no one has an objection to this patch, can I get a
Acked-by and
can we queue it up for upstream.
Regards,
Bhupesh
-Original Message-
From: Sharma Bhupesh-B45370
Sent: Tuesday, July 23, 2013 2:00 PM
To: u-boot@lists.denx.de; Fleming Andy-AFLEMING;
joe.hershber...@gmail.com
Cc: Sharma Bhupesh-B45370
Subject: RE: [PATCH 1/1] net: phy/realtek: Add support for RTL8211DN and
RTL8211E phy modules
Hi Andy, Joe,
This patch adds support for Realtek PHY modules RTL8211DN and RTL8211E
(variants: RTL8211E-VB-CG, RTL8211E-VL-CG, RTL8211EG-VB-CG), which can
be found on Freescale's T1040RDB boards.
To make the driver more generic across 8211 family, a generic name
8211x is added for macros and function names.
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
Can you please review this patch and let me know if these changes seem
suitable to you.
Thanks for your help.
Regards,
Bhupesh
---
drivers/net/phy/realtek.c | 77
+++--
--
1 file changed, 51 insertions(+), 26 deletions(-)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index
b7e2753..b971456 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -26,18 +26,18 @@
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
-/* RTL8211B PHY Status Register */
-#define MIIM_RTL8211B_PHY_STATUS 0x11
-#define MIIM_RTL8211B_PHYSTAT_SPEED0xc000
-#define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000
-#define MIIM_RTL8211B_PHYSTAT_100 0x4000
-#define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000
-#define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800
-#define MIIM_RTL8211B_PHYSTAT_LINK 0x0400
-
-
-/* RealTek RTL8211B */
-static int rtl8211b_config(struct phy_device *phydev)
+/* RTL8211x PHY Status Register */
+#define MIIM_RTL8211x_PHY_STATUS 0x11
+#define MIIM_RTL8211x_PHYSTAT_SPEED0xc000
+#define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
+#define MIIM_RTL8211x_PHYSTAT_100 0x4000
+#define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
+#define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
+#define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
+
+
+/* RealTek RTL8211x */
+static int rtl8211x_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
@@ -46,20 +46,20 @@ static int rtl8211b_config(struct phy_device
*phydev)
return 0;
}
-static int rtl8211b_parse_status(struct phy_device *phydev)
+static int rtl8211x_parse_status(struct phy_device *phydev)
{
unsigned int speed;
unsigned int mii_reg;
- mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
MIIM_RTL8211B_PHY_STATUS);
+ mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
MIIM_RTL8211x_PHY_STATUS);
- if (!(mii_reg MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
+ if (!(mii_reg MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
int i = 0;
/* in case of timeout -link is cleared */
phydev-link = 1;
puts(Waiting for PHY realtime link);
- while (!(mii_reg MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
+ while (!(mii_reg MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
/* Timeout reached ? */
if (i PHY_AUTONEGOTIATE_TIMEOUT) {
puts( TIMEOUT !\n);
@@ -71,29 +71,29 @@ static int rtl8211b_parse_status(struct phy_device
*phydev)
putc('.');
udelay(1000); /* 1 ms */
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
- MIIM_RTL8211B_PHY_STATUS);
+ MIIM_RTL8211x_PHY_STATUS);
}
puts( done\n);
udelay(50); /* another 500 ms (results in faster
booting) */
} else {
- if (mii_reg MIIM_RTL8211B_PHYSTAT_LINK)
+ if (mii_reg MIIM_RTL8211x_PHYSTAT_LINK)
phydev-link = 1;
else
phydev-link = 0;
}
- if (mii_reg MIIM_RTL8211B_PHYSTAT_DUPLEX)
+ if (mii_reg MIIM_RTL8211x_PHYSTAT_DUPLEX)
phydev-duplex = DUPLEX_FULL;
else
phydev-duplex = DUPLEX_HALF;
- speed = (mii_reg MIIM_RTL8211B_PHYSTAT_SPEED);
+ speed = (mii_reg MIIM_RTL8211x_PHYSTAT_SPEED);
switch (speed) {
- case MIIM_RTL8211B_PHYSTAT_GBIT:
+ case MIIM_RTL8211x_PHYSTAT_GBIT:
phydev-speed = SPEED_1000;
break;
- case MIIM_RTL8211B_PHYSTAT_100:
+ case MIIM_RTL8211x_PHYSTAT_100:
phydev-speed = SPEED_100;
break;
default:
@@ -103,28 +103,53 @@ static int rtl8211b_parse_status(struct
phy_device
*phydev)
return 0;
}
-static int rtl8211b_startup(struct phy_device *phydev)
+static int
Re: [U-Boot] [PATCH v2 2/6] drivers/power/pmic: Add tps65217 driver
On Wed, 14 Aug 2013 11:57:06 -0400 Tom Rini tr...@ti.com wrote:
On Wed, Aug 14, 2013 at 05:08:12PM +0200, Lukasz Majewski wrote:
Hi Tom, Greg
From: Greg Guyotte gguyo...@ti.com
Add a driver for the TPS65217 PMIC that is found in the Beaglebone
family of boards.
Signed-off-by: Greg Guyotte gguyo...@ti.com
[trini: Split and rework Greg's changes into new drivers/power
framework]
Signed-off-by: Tom Rini tr...@ti.com
---
Changes in v2:
- Address Dan's comments
- Change to SPDX license tag
- Add TRM link in the header
Signed-off-by: Tom Rini tr...@ti.com
---
drivers/power/pmic/Makefile|1 +
drivers/power/pmic/pmic_tps65217.c | 109
include/power/tps65217.h | 79
++ 3 files changed, 189 insertions(+)
create mode 100644 drivers/power/pmic/pmic_tps65217.c create mode
100644 include/power/tps65217.h
diff --git a/drivers/power/pmic/Makefile
b/drivers/power/pmic/Makefile index f054470..ac2b625 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -13,6 +13,7 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
COBJS:= $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/power/pmic/pmic_tps65217.c
b/drivers/power/pmic/pmic_tps65217.c new file mode 100644
index 000..36e9024
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65217.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, www.ti.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+#include power/tps65217.h
+
+/**
+ * tps65217_reg_read() - Generic function that can read a
TPS65217 register
+ * @src_reg: Source register address
+ * @src_val: Address of destination variable
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65217_reg_read(uchar src_reg, uchar *src_val)
+{
+ return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val,
1);
Would it be possible to comply with pmic driver model?
It can be found at ./drivers/power/power_core.c
At the high level, not yet. We don't have battery support (but fixing
that to be optional in the core wouldn't be hard) but the general pmic
code assumes one pmic charger per binary.
As fair as I remember, there is no such assumption. The pmic driver
allocates each pmic object separately (which can be distinguished by
unique name - also many instances of the same devices are possible).
Each power device is treated in the same way (described by struct
pmic), no matter if it is a battery, charger, PMIC or MUIC.
Then each reference is done via struct pmic *p pointer. The charger is
not needed to use the generic pmic_reg_write().
The tps65217_reg_read() method is used at board/ti/am335x/board.c -
[PATCH v2 6/6] am335x_evm: am33xx_spl_board_init function and scale
core frequency
It is a similar use to pmic_init_max8997(void) defined
at board/samsung/trats/trats.c
We need both in the same
binary (since we decide at run-time if it's one of the boards with
65910 or 65217).
The pmic core can register both devices, then with OF decide to which
one refer with e.g. p-name field.
Moreover the generic function for reading/writing data to/from pmic
is already defined at ./drivers/power/power_{i2c|spi}.c
Maybe it would be possible to use/modify the already available code?
Without the MAX family datasheets handy, I'm not sure how exactly the
tx_num stuff maps to the password concept the TI parts have. Skimming
the kernel mfd drivers implies to me that logic ends up being per-chip
(or at least vendor).
We have spent some time with Stefano to provide correct read/write for
the following:
- 1,2,3 bytes transfers
- little + big endian data format support
- support for SPI and I2C.
This is already implemented at pmic_reg_write().
[snip]
+/**
+ * tps65217_voltage_update() - Function to change a voltage
level, as this
+ * is a multi-step process.
+ * @dc_cntrl_reg: DC voltage control register to
change.
+ * @volt_sel: New value for the voltage
register
+ * @return: 0 for success, not 0 on
failure.
+ */
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
Maybe pmic_set_output() method from ./drivers/power/power_core.c
can be reused?
I'm not sure.
At least we shall give it a try.
[snip]
+#define TPS65217_SEQ60x1E
Shouldn't the above registers be defined as enum?
For example at
Re: [U-Boot] [PATCH 1/1] net: phy/realtek: Add support for RTL8211DN and RTL8211E phy modules
On 08/14/2013 01:30 PM, Sharma Bhupesh-B45370 wrote: Hi York, I guess with Andy no longer there as FSL u-boot maintainer, will the patch below go through you or Joe. If no one has an objection to this patch, can I get a Acked-by and can we queue it up for upstream. Acked-by: York Sun york...@freescale.com This patch doesn't involve mpc85xx or mpc86xx. I don't see why it should go into 85xx tree. Do you have other patch depending on it? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] net: phy/realtek: Add support for RTL8211DN and RTL8211E phy modules
-Original Message- From: sun york-R58495 Sent: Thursday, August 15, 2013 2:29 AM To: Sharma Bhupesh-B45370 Cc: 'u-boot@lists.denx.de'; 'joe.hershber...@gmail.com' Subject: Re: [PATCH 1/1] net: phy/realtek: Add support for RTL8211DN and RTL8211E phy modules On 08/14/2013 01:30 PM, Sharma Bhupesh-B45370 wrote: Hi York, I guess with Andy no longer there as FSL u-boot maintainer, will the patch below go through you or Joe. If no one has an objection to this patch, can I get a Acked-by and can we queue it up for upstream. Acked-by: York Sun york...@freescale.com This patch doesn't involve mpc85xx or mpc86xx. I don't see why it should go into 85xx tree. Do you have other patch depending on it? I believe this patch is completely independent of the mpc series. As Andy was the original author of the RTL phy module(s) driver in u-boot, I was expecting that I needed a Acked-by from him before this patch can be taken up via Andy's/Joe's tree. As far as I remember, Joe has already mentioned that this patch looks 'good' to him. Joe, if you have no objection to the patch, can you please pick the same in your tree (now that York has already Acked the same). Thanks, Bhupesh York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5] ARM: mxs: Added application UART driver
The driver makes it possible to use an application UART as
the U-Boot output console for Freescale i.MX23/i.MX28 devices.
Signed-off-by: Andreas Wass andreas.w...@dalelven.com
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Marek Vasut ma...@denx.de
---
Changes for v2:
- Added comment that regs-uartapp.h is pulled from LTIB
- BM_ prefixes removed and _MASK suffixes added instead
- BP_ prefixes removed and _OFFSET suffixes added instead
- BF_ defines removed altogether
- CONFIG_MXS_AUART_CLK renamed to MXS_AUART_CLK and guarding ifndef removed
- Added comments describing what is set and unset during init of driver
- Added newline that was accidently removed from serial.c
Changes for v3:
- All BV_ values are now on the form (value something)
- BV_ prefix removed and double underscore substituted with a single
- File comment of mxs_auart.c now attributes what the driver is based on
- Uses gd-baudrate instead of CONFIG_BAUDRATE
- If gd-baudrate is 0 it reverts back to CONFIG_BAUDRATE
- Checks the validity of the div value calculated when setting the baudrate
- Magic numbers are now defines instead
- Cleanup of comments
- Cleanup of commit message
Changes for v4:
- Fixed UARTAPP_LINECTRL2_WLEN_*BITS values
Changes for v5:
- Removed all RSVD values from regs-uartapp.h
- 0x (and similar) turned into 0x (and similar)
- Removed all bitshifts by 0
- All masks with non-zero shifting are now on the form (value shift)
arch/arm/include/asm/arch-mxs/regs-uartapp.h | 220 +++
drivers/serial/Makefile | 1 +
drivers/serial/mxs_auart.c | 151 ++
drivers/serial/serial.c | 2 +
4 files changed, 374 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mxs/regs-uartapp.h
create mode 100644 drivers/serial/mxs_auart.c
diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h
b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
new file mode 100644
index 000..7ceb810
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
@@ -0,0 +1,220 @@
+/*
+ * Freescale MXS UARTAPP Register Definitions
+ *
+ * Copyright (C) 2013 Andreas Wass andreas.w...@dalelven.com
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM___MXS_UARTAPP_H
+#define __ARCH_ARM___MXS_UARTAPP_H
+
+#include asm/imx-common/regs-common.h
+
+#ifndef __ASSEMBLY__
+struct mxs_uartapp_regs {
+ mxs_reg_32(hw_uartapp_ctrl0)
+ mxs_reg_32(hw_uartapp_ctrl1)
+ mxs_reg_32(hw_uartapp_ctrl2)
+ mxs_reg_32(hw_uartapp_linectrl)
+ mxs_reg_32(hw_uartapp_linectrl2)
+ mxs_reg_32(hw_uartapp_intr)
+ mxs_reg_32(hw_uartapp_data)
+ mxs_reg_32(hw_uartapp_stat)
+ mxs_reg_32(hw_uartapp_debug)
+ mxs_reg_32(hw_uartapp_version)
+ mxs_reg_32(hw_uartapp_autobaud)
+};
+#endif
+
+#define UARTAPP_CTRL0_SFTRST_MASK (1 31)
+#define UARTAPP_CTRL0_CLKGATE_MASK (1 30)
+#define UARTAPP_CTRL0_RUN_MASK (1 29)
+#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 28)
+#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 27)
+#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
+#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF 16)
+#define UARTAPP_CTRL0_XFER_COUNT_OFFSET0
+#define UARTAPP_CTRL0_XFER_COUNT_MASK 0x
+
+#define UARTAPP_CTRL1_RUN_MASK (1 28)
+
+#define UARTAPP_CTRL1_XFER_COUNT_OFFSET0
+#define UARTAPP_CTRL1_XFER_COUNT_MASK 0x
+
+#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 31)
+#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 30)
+#define UARTAPP_CTRL2_INVERT_TX_MASK (1 29)
+#define UARTAPP_CTRL2_INVERT_RX_MASK (1 28)
+#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 27)
+#define UARTAPP_CTRL2_DMAONERR_MASK(1 26)
+#define UARTAPP_CTRL2_TXDMAE_MASK (1 25)
+#define UARTAPP_CTRL2_RXDMAE_MASK (1 24)
+#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
+#define UARTAPP_CTRL2_RXIFLSEL_MASK(0x7 20)
+
+#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF(0x2 20)
+#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 20)
+#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID5(0x5 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID6(0x6 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID7(0x7
Re: [U-Boot] [PATCH v5] ARM: mxs: Added application UART driver
Dear Andreas Wass, The driver makes it possible to use an application UART as the U-Boot output console for Freescale i.MX23/i.MX28 devices. Signed-off-by: Andreas Wass andreas.w...@dalelven.com Cc: Fabio Estevam fabio.este...@freescale.com Cc: Marek Vasut ma...@denx.de --- Changes for v2: - Added comment that regs-uartapp.h is pulled from LTIB - BM_ prefixes removed and _MASK suffixes added instead - BP_ prefixes removed and _OFFSET suffixes added instead - BF_ defines removed altogether - CONFIG_MXS_AUART_CLK renamed to MXS_AUART_CLK and guarding ifndef removed - Added comments describing what is set and unset during init of driver - Added newline that was accidently removed from serial.c Changes for v3: - All BV_ values are now on the form (value something) - BV_ prefix removed and double underscore substituted with a single - File comment of mxs_auart.c now attributes what the driver is based on - Uses gd-baudrate instead of CONFIG_BAUDRATE - If gd-baudrate is 0 it reverts back to CONFIG_BAUDRATE - Checks the validity of the div value calculated when setting the baudrate - Magic numbers are now defines instead - Cleanup of comments - Cleanup of commit message Changes for v4: - Fixed UARTAPP_LINECTRL2_WLEN_*BITS values Changes for v5: - Removed all RSVD values from regs-uartapp.h - 0x (and similar) turned into 0x (and similar) - Removed all bitshifts by 0 - All masks with non-zero shifting are now on the form (value shift) arch/arm/include/asm/arch-mxs/regs-uartapp.h | 220 +++ drivers/serial/Makefile | 1 + drivers/serial/mxs_auart.c | 151 ++ drivers/serial/serial.c | 2 + 4 files changed, 374 insertions(+) create mode 100644 arch/arm/include/asm/arch-mxs/regs-uartapp.h create mode 100644 drivers/serial/mxs_auart.c Acked-by: Marek Vasut ma...@denx.de Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] net: phy/realtek: Add support for RTL8211DN and RTL8211E phy modules
On Wed, Aug 14, 2013 at 4:08 PM, Sharma Bhupesh-B45370 b45...@freescale.com wrote: -Original Message- From: sun york-R58495 Sent: Thursday, August 15, 2013 2:29 AM To: Sharma Bhupesh-B45370 Cc: 'u-boot@lists.denx.de'; 'joe.hershber...@gmail.com' Subject: Re: [PATCH 1/1] net: phy/realtek: Add support for RTL8211DN and RTL8211E phy modules On 08/14/2013 01:30 PM, Sharma Bhupesh-B45370 wrote: Hi York, I guess with Andy no longer there as FSL u-boot maintainer, will the patch below go through you or Joe. If no one has an objection to this patch, can I get a Acked-by and can we queue it up for upstream. Acked-by: York Sun york...@freescale.com This patch doesn't involve mpc85xx or mpc86xx. I don't see why it should go into 85xx tree. Do you have other patch depending on it? I believe this patch is completely independent of the mpc series. As Andy was the original author of the RTL phy module(s) driver in u-boot, I was expecting that I needed a Acked-by from him before this patch can be taken up via Andy's/Joe's tree. As far as I remember, Joe has already mentioned that this patch looks 'good' to him. Joe, if you have no objection to the patch, can you please pick the same in your tree (now that York has already Acked the same). OK... I'll pull it into net this week. -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import
York, I had checked all the patch and I am sure there is only this patch almost forgotten. I don't know how to do. Need I send the patch again or other way? Thanks. -Original Message- From: sun york-R58495 Sent: Wednesday, August 14, 2013 11:42 PM To: Zhang Ying-B40530 Cc: Tom Rini; Wood Scott-B07421; u-boot@lists.denx.de; aflem...@gmail.com Subject: Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import On 08/14/2013 06:48 AM, Tom Rini wrote: On 08/13/2013 10:31 PM, Zhang Ying-B40530 wrote: Hi, Tom, This patch hasn't been applied? I think it should be applied early and it is needed by other patches of this set. Thanks. I expect that as part of the overall series, once ready, York will take this and include it in his pull request, which is why I've given it my acked-by. Ying, This patch fell through the crack. I didn't see it because it was marked as superseded. Please check your other patches. You can delegate them to me. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/p1010rdb: remove CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK was needed only on obsolete P1010RDB Rev.B non-formal board, not reproduced on P1010RDB Rev.C and new P1010RDB-PB, now it's no longer needed. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/include/asm/config_mpc85xx.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index e5dee85..dfb2d17 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -139,7 +139,6 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_NUM_USB_CTRLS 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/sec: Add workaround for SEC A-003571
Multiple read/write transactions initiated by security
engine may cause system to hang.
Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4
arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 +-
arch/powerpc/include/asm/config_mpc85xx.h | 1 +
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index e6d1023..2e1fc06 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -348,6 +348,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts(Work-around for Erratum A006593 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
+ if (IS_SVR_REV(svr, 1, 0))
+ puts(Work-around for Erratum A003571 enabled\n);
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 7b81f5d..be09009 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -444,7 +444,9 @@ int cpu_init_r(void)
extern int spin_table_compat;
const char *spin;
#endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
+ ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
@@ -634,6 +636,12 @@ skip_l2:
fsl_serdes_init();
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
+#define MCFGR_AXIPIPE 0x00f0
+ if (IS_SVR_REV(svr, 1, 0))
+ clrbits_be32(sec-mcfgr, MCFGR_AXIPIPE);
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0)) {
int i;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 86c2598..cc6e405 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -149,6 +149,7 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_ISBC_VER1
--
1.8.0
___
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Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import
On Aug 14, 2013, at 7:25 PM, Zhang Ying-B40530 wrote: York, I had checked all the patch and I am sure there is only this patch almost forgotten. I don't know how to do. Need I send the patch again or other way? Thanks. No need to resend. I can mark it. Just want to be sure there isn't a newer version hiding somewhere. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import
Hi, York, I see. I am sure there isn't newer version. -Original Message- From: sun york-R58495 Sent: Thursday, August 15, 2013 10:42 AM To: Zhang Ying-B40530 Cc: Tom Rini; Wood Scott-B07421; u-boot@lists.denx.de; Andy Fleming; Xie Xiaobo-R63061 Subject: Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import On Aug 14, 2013, at 7:25 PM, Zhang Ying-B40530 wrote: York, I had checked all the patch and I am sure there is only this patch almost forgotten. I don't know how to do. Need I send the patch again or other way? Thanks. No need to resend. I can mark it. Just want to be sure there isn't a newer version hiding somewhere. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e.
On 07/09/2013 02:43 AM, Naumann Andreas wrote:
In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in
Certain Configurations' of the TI Errata it is recommended to use certain
div/mult values for the DPLL5 clock setup.
So far u-boot used the old 34xx values, so I added the errata recommended
values specificly for 36xx init only.
Also, the FSEL registers exist no longer, so removed them from init.
Tested this on a AM3703 board with 19.2MHz oscillator, which previously couldnt
lock the dpll5 (kernel complained). As a consequence the EHCI USB port wasnt
usable in U-Boot and kernel. With this patch, kernel panics disappear and USB
working fine in u-boot and kernel.
Signed-off-by: Andreas Naumann anaum...@ultratronik.de
While this patch works with Linux that has been patched for this
erratum, it will cause problems with some unpatched versions of Linux.
In particular, this patch sets CM_CLKSEL4_PLL to generate (nearly)
960MHz, and CM_CLKSEL5_PLL to divide by 8 to produce the required
120MHz, as recommended by sprz318e advisory 2.1.
Version 3.5 of Linux, and possibly others, configure CM_CLKSEL4_PLL
(named dpll5_ck) to generate 120MHz and leaves CM_CLKSEL5_PLL
unmodified since its clock (named dpll5_m2_ck) does not support set
rate. If u-boot has configured a divisor of 8, the result is that the
actual clock speed is 15MHz and USB does not work.
Not sure how this ought to be resolved; in my case I'm going to skip the
u-boot patch and just use the Linux patch.
Peter
---
arch/arm/cpu/armv7/omap3/clock.c | 20 +++-
arch/arm/cpu/armv7/omap3/lowlevel_init.S | 18 ++
arch/arm/include/asm/arch-omap3/clocks_omap3.h | 22 ++
3 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 81cc859..68833ba 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -491,6 +491,24 @@ static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
wait_on_value(ST_PERIPH_CLK, 2, prcm_base-idlest_ckgen, LDELAY);
}
+static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr = ptr + clk_index;
+
+ /* PER2 DPLL (DPLL5) */
+ sr32(prcm_base-clken2_pll, 0, 3, PLL_STOP);
+ wait_on_value(1, 0, prcm_base-idlest2_ckgen, LDELAY);
+ sr32(prcm_base-clksel5_pll, 0, 5, ptr-m2); /* set M2 (usbtll_fck) */
+ sr32(prcm_base-clksel4_pll, 8, 11, ptr-m); /* set m (11-bit
multiplier) */
+ sr32(prcm_base-clksel4_pll, 0, 7, ptr-n); /* set n (7-bit divider)*/
+ sr32(prcm_base-clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(1, 1, prcm_base-idlest2_ckgen, LDELAY);
+}
+
static void mpu_init_36xx(u32 sil_index, u32 clk_index)
{
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
@@ -595,7 +613,7 @@ void prcm_init(void)
dpll3_init_36xx(0, clk_index);
dpll4_init_36xx(0, clk_index);
- dpll5_init_34xx(0, clk_index);
+ dpll5_init_36xx(0, clk_index);
iva_init_36xx(0, clk_index);
mpu_init_36xx(0, clk_index);
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index eacfef8..66a1b48 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -480,6 +480,19 @@ per_36x_dpll_param:
.word 26000,432, 12, 9, 16, 9, 4, 3, 1
.word 38400,360, 15, 9, 16, 5, 4, 3, 1
+per2_36x_dpll_param:
+/* 12MHz */
+.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
+/* 13MHz */
+.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
+/* 19.2MHz */
+.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
+/* 26MHz */
+.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
+/* 38.4MHz */
+.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
+
+
ENTRY(get_36x_mpu_dpll_param)
adr r0, mpu_36x_dpll_param
mov pc, lr
@@ -499,3 +512,8 @@ ENTRY(get_36x_per_dpll_param)
adr r0, per_36x_dpll_param
mov pc, lr
ENDPROC(get_36x_per_dpll_param)
+
+ENTRY(get_36x_per2_dpll_param)
+ adr r0, per2_36x_dpll_param
+ mov pc, lr
+ENDPROC(get_36x_per2_dpll_param)
diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h
b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
index 5925ac4..59e61e8 100644
--- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h
+++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
@@ -336,4 +336,26 @@
#define PER_36XX_FSEL_38P40x07
#define PER_36XX_M2_38P4 0x09
+/* 36XX PER2 DPLL */
+
+#define PER2_36XX_M_12 0x50
+#define
